core/stdarch/crates/core_arch/src/powerpc/
altivec.rs

1//! PowerPC AltiVec intrinsics.
2//!
3//! AltiVec is a brandname trademarked by Freescale (previously Motorola) for
4//! the standard `Category:Vector` part of the Power ISA v.2.03 specification.
5//! This Category is also known as VMX (used by IBM), and "Velocity Engine" (a
6//! brand name previously used by Apple).
7//!
8//! The references are: [POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA
9//! NVlink)] and [POWER ISA v3.0B (for POWER9)].
10//!
11//! [POWER ISA v2.07B (for POWER8 & POWER8 with NVIDIA NVlink)]: https://ibm.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u
12//! [POWER ISA v3.0B (for POWER9)]: https://ibm.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv
13
14#![allow(non_camel_case_types)]
15
16use crate::{core_arch::simd::*, intrinsics::simd::*, mem, mem::transmute};
17
18#[cfg(test)]
19use stdarch_test::assert_instr;
20
21use super::macros::*;
22
23types! {
24    #![unstable(feature = "stdarch_powerpc", issue = "111145")]
25
26    /// PowerPC-specific 128-bit wide vector of sixteen packed `i8`
27    pub struct vector_signed_char(16 x i8);
28    /// PowerPC-specific 128-bit wide vector of sixteen packed `u8`
29    pub struct vector_unsigned_char(16 x u8);
30
31    /// PowerPC-specific 128-bit wide vector mask of sixteen packed elements
32    pub struct vector_bool_char(16 x i8);
33    /// PowerPC-specific 128-bit wide vector of eight packed `i16`
34    pub struct vector_signed_short(8 x i16);
35    /// PowerPC-specific 128-bit wide vector of eight packed `u16`
36    pub struct vector_unsigned_short(8 x u16);
37    /// PowerPC-specific 128-bit wide vector mask of eight packed elements
38    pub struct vector_bool_short(8 x i16);
39    // pub struct vector_pixel(???);
40    /// PowerPC-specific 128-bit wide vector of four packed `i32`
41    pub struct vector_signed_int(4 x i32);
42    /// PowerPC-specific 128-bit wide vector of four packed `u32`
43    pub struct vector_unsigned_int(4 x u32);
44    /// PowerPC-specific 128-bit wide vector mask of four packed elements
45    pub struct vector_bool_int(4 x i32);
46    /// PowerPC-specific 128-bit wide vector of four packed `f32`
47    pub struct vector_float(4 x f32);
48}
49
50#[unstable(feature = "stdarch_powerpc", issue = "111145")]
51impl From<m8x16> for vector_bool_char {
52    #[inline]
53    fn from(value: m8x16) -> Self {
54        unsafe { transmute(value) }
55    }
56}
57
58#[unstable(feature = "stdarch_powerpc", issue = "111145")]
59impl From<vector_bool_char> for m8x16 {
60    #[inline]
61    fn from(value: vector_bool_char) -> Self {
62        unsafe { transmute(value) }
63    }
64}
65
66#[unstable(feature = "stdarch_powerpc", issue = "111145")]
67impl From<m16x8> for vector_bool_short {
68    #[inline]
69    fn from(value: m16x8) -> Self {
70        unsafe { transmute(value) }
71    }
72}
73
74#[unstable(feature = "stdarch_powerpc", issue = "111145")]
75impl From<vector_bool_short> for m16x8 {
76    #[inline]
77    fn from(value: vector_bool_short) -> Self {
78        unsafe { transmute(value) }
79    }
80}
81
82#[unstable(feature = "stdarch_powerpc", issue = "111145")]
83impl From<m32x4> for vector_bool_int {
84    #[inline]
85    fn from(value: m32x4) -> Self {
86        unsafe { transmute(value) }
87    }
88}
89
90#[unstable(feature = "stdarch_powerpc", issue = "111145")]
91impl From<vector_bool_int> for m32x4 {
92    #[inline]
93    fn from(value: vector_bool_int) -> Self {
94        unsafe { transmute(value) }
95    }
96}
97
98#[allow(improper_ctypes)]
99unsafe extern "C" {
100    #[link_name = "llvm.ppc.altivec.lvx"]
101    fn lvx(p: *const i8) -> vector_unsigned_int;
102
103    #[link_name = "llvm.ppc.altivec.lvebx"]
104    fn lvebx(p: *const i8) -> vector_signed_char;
105    #[link_name = "llvm.ppc.altivec.lvehx"]
106    fn lvehx(p: *const i8) -> vector_signed_short;
107    #[link_name = "llvm.ppc.altivec.lvewx"]
108    fn lvewx(p: *const i8) -> vector_signed_int;
109
110    #[link_name = "llvm.ppc.altivec.lvxl"]
111    fn lvxl(p: *const i8) -> vector_unsigned_int;
112
113    #[link_name = "llvm.ppc.altivec.stvx"]
114    fn stvx(a: vector_signed_int, p: *const i8);
115
116    #[link_name = "llvm.ppc.altivec.stvebx"]
117    fn stvebx(a: vector_signed_char, p: *const i8);
118    #[link_name = "llvm.ppc.altivec.stvehx"]
119    fn stvehx(a: vector_signed_short, p: *const i8);
120    #[link_name = "llvm.ppc.altivec.stvewx"]
121    fn stvewx(a: vector_signed_int, p: *const i8);
122
123    #[link_name = "llvm.ppc.altivec.stvxl"]
124    fn stvxl(a: vector_signed_int, p: *const i8);
125
126    #[link_name = "llvm.ppc.altivec.vperm"]
127    fn vperm(
128        a: vector_signed_int,
129        b: vector_signed_int,
130        c: vector_unsigned_char,
131    ) -> vector_signed_int;
132    #[link_name = "llvm.ppc.altivec.vmhaddshs"]
133    fn vmhaddshs(
134        a: vector_signed_short,
135        b: vector_signed_short,
136        c: vector_signed_short,
137    ) -> vector_signed_short;
138    #[link_name = "llvm.ppc.altivec.vmhraddshs"]
139    fn vmhraddshs(
140        a: vector_signed_short,
141        b: vector_signed_short,
142        c: vector_signed_short,
143    ) -> vector_signed_short;
144    #[link_name = "llvm.ppc.altivec.vmsumuhs"]
145    fn vmsumuhs(
146        a: vector_unsigned_short,
147        b: vector_unsigned_short,
148        c: vector_unsigned_int,
149    ) -> vector_unsigned_int;
150    #[link_name = "llvm.ppc.altivec.vmsumshs"]
151    fn vmsumshs(
152        a: vector_signed_short,
153        b: vector_signed_short,
154        c: vector_signed_int,
155    ) -> vector_signed_int;
156    #[link_name = "llvm.ppc.altivec.vmsumubm"]
157    fn vmsumubm(
158        a: vector_unsigned_char,
159        b: vector_unsigned_char,
160        c: vector_unsigned_int,
161    ) -> vector_unsigned_int;
162    #[link_name = "llvm.ppc.altivec.vmsummbm"]
163    fn vmsummbm(
164        a: vector_signed_char,
165        b: vector_unsigned_char,
166        c: vector_signed_int,
167    ) -> vector_signed_int;
168    #[link_name = "llvm.ppc.altivec.vmsumuhm"]
169    fn vmsumuhm(
170        a: vector_unsigned_short,
171        b: vector_unsigned_short,
172        c: vector_unsigned_int,
173    ) -> vector_unsigned_int;
174    #[link_name = "llvm.ppc.altivec.vmsumshm"]
175    fn vmsumshm(
176        a: vector_signed_short,
177        b: vector_signed_short,
178        c: vector_signed_int,
179    ) -> vector_signed_int;
180    #[link_name = "llvm.ppc.altivec.vsum2sws"]
181    fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
182    #[link_name = "llvm.ppc.altivec.vsum4ubs"]
183    fn vsum4ubs(a: vector_unsigned_char, b: vector_unsigned_int) -> vector_unsigned_int;
184    #[link_name = "llvm.ppc.altivec.vsum4sbs"]
185    fn vsum4sbs(a: vector_signed_char, b: vector_signed_int) -> vector_signed_int;
186    #[link_name = "llvm.ppc.altivec.vsum4shs"]
187    fn vsum4shs(a: vector_signed_short, b: vector_signed_int) -> vector_signed_int;
188    #[link_name = "llvm.ppc.altivec.vmuleub"]
189    fn vmuleub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_short;
190    #[link_name = "llvm.ppc.altivec.vmulesb"]
191    fn vmulesb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short;
192    #[link_name = "llvm.ppc.altivec.vmuleuh"]
193    fn vmuleuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_int;
194    #[link_name = "llvm.ppc.altivec.vmulesh"]
195    fn vmulesh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;
196    #[link_name = "llvm.ppc.altivec.vmuloub"]
197    fn vmuloub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_short;
198    #[link_name = "llvm.ppc.altivec.vmulosb"]
199    fn vmulosb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short;
200    #[link_name = "llvm.ppc.altivec.vmulouh"]
201    fn vmulouh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_int;
202    #[link_name = "llvm.ppc.altivec.vmulosh"]
203    fn vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;
204
205    #[link_name = "llvm.smax.v16i8"]
206    fn vmaxsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
207    #[link_name = "llvm.smax.v8i16"]
208    fn vmaxsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
209    #[link_name = "llvm.smax.v4i32"]
210    fn vmaxsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
211
212    #[link_name = "llvm.umax.v16i8"]
213    fn vmaxub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
214    #[link_name = "llvm.umax.v8i16"]
215    fn vmaxuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
216    #[link_name = "llvm.umax.v4i32"]
217    fn vmaxuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
218
219    #[link_name = "llvm.smin.v16i8"]
220    fn vminsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
221    #[link_name = "llvm.smin.v8i16"]
222    fn vminsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
223    #[link_name = "llvm.smin.v4i32"]
224    fn vminsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
225
226    #[link_name = "llvm.umin.v16i8"]
227    fn vminub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
228    #[link_name = "llvm.umin.v8i16"]
229    fn vminuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
230    #[link_name = "llvm.umin.v4i32"]
231    fn vminuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
232
233    #[link_name = "llvm.ppc.altivec.vsubsbs"]
234    fn vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
235    #[link_name = "llvm.ppc.altivec.vsubshs"]
236    fn vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
237    #[link_name = "llvm.ppc.altivec.vsubsws"]
238    fn vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
239
240    #[link_name = "llvm.ppc.altivec.vsububs"]
241    fn vsububs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
242    #[link_name = "llvm.ppc.altivec.vsubuhs"]
243    fn vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
244    #[link_name = "llvm.ppc.altivec.vsubuws"]
245    fn vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
246
247    #[link_name = "llvm.ppc.altivec.vsubcuw"]
248    fn vsubcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
249
250    #[link_name = "llvm.ppc.altivec.vaddcuw"]
251    fn vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
252
253    #[link_name = "llvm.ppc.altivec.vaddsbs"]
254    fn vaddsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
255    #[link_name = "llvm.ppc.altivec.vaddshs"]
256    fn vaddshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
257    #[link_name = "llvm.ppc.altivec.vaddsws"]
258    fn vaddsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
259
260    #[link_name = "llvm.ppc.altivec.vaddubs"]
261    fn vaddubs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
262    #[link_name = "llvm.ppc.altivec.vadduhs"]
263    fn vadduhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
264    #[link_name = "llvm.ppc.altivec.vadduws"]
265    fn vadduws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
266
267    #[link_name = "llvm.ppc.altivec.vavgsb"]
268    fn vavgsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
269    #[link_name = "llvm.ppc.altivec.vavgsh"]
270    fn vavgsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
271    #[link_name = "llvm.ppc.altivec.vavgsw"]
272    fn vavgsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
273
274    #[link_name = "llvm.ppc.altivec.vavgub"]
275    fn vavgub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
276    #[link_name = "llvm.ppc.altivec.vavguh"]
277    fn vavguh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
278    #[link_name = "llvm.ppc.altivec.vavguw"]
279    fn vavguw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
280
281    #[link_name = "llvm.ppc.altivec.vcmpbfp"]
282    fn vcmpbfp(a: vector_float, b: vector_float) -> vector_signed_int;
283
284    #[link_name = "llvm.ppc.altivec.vcmpequb"]
285    fn vcmpequb(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char;
286    #[link_name = "llvm.ppc.altivec.vcmpequh"]
287    fn vcmpequh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short;
288    #[link_name = "llvm.ppc.altivec.vcmpequw"]
289    fn vcmpequw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int;
290
291    #[link_name = "llvm.ppc.altivec.vcmpneb"]
292    fn vcmpneb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char;
293    #[link_name = "llvm.ppc.altivec.vcmpneh"]
294    fn vcmpneh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short;
295    #[link_name = "llvm.ppc.altivec.vcmpnew"]
296    fn vcmpnew(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int;
297
298    #[link_name = "llvm.ppc.altivec.vcmpgefp"]
299    fn vcmpgefp(a: vector_float, b: vector_float) -> vector_bool_int;
300
301    #[link_name = "llvm.ppc.altivec.vcmpgtub"]
302    fn vcmpgtub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char;
303    #[link_name = "llvm.ppc.altivec.vcmpgtuh"]
304    fn vcmpgtuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short;
305    #[link_name = "llvm.ppc.altivec.vcmpgtuw"]
306    fn vcmpgtuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int;
307
308    #[link_name = "llvm.ppc.altivec.vcmpgtsb"]
309    fn vcmpgtsb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char;
310    #[link_name = "llvm.ppc.altivec.vcmpgtsh"]
311    fn vcmpgtsh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short;
312    #[link_name = "llvm.ppc.altivec.vcmpgtsw"]
313    fn vcmpgtsw(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int;
314
315    #[link_name = "llvm.ppc.altivec.vexptefp"]
316    fn vexptefp(a: vector_float) -> vector_float;
317
318    #[link_name = "llvm.ppc.altivec.vcmpequb.p"]
319    fn vcmpequb_p(cr: i32, a: vector_unsigned_char, b: vector_unsigned_char) -> i32;
320    #[link_name = "llvm.ppc.altivec.vcmpequh.p"]
321    fn vcmpequh_p(cr: i32, a: vector_unsigned_short, b: vector_unsigned_short) -> i32;
322    #[link_name = "llvm.ppc.altivec.vcmpequw.p"]
323    fn vcmpequw_p(cr: i32, a: vector_unsigned_int, b: vector_unsigned_int) -> i32;
324
325    #[link_name = "llvm.ppc.altivec.vcmpeqfp.p"]
326    fn vcmpeqfp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
327
328    #[link_name = "llvm.ppc.altivec.vcmpgtub.p"]
329    fn vcmpgtub_p(cr: i32, a: vector_unsigned_char, b: vector_unsigned_char) -> i32;
330    #[link_name = "llvm.ppc.altivec.vcmpgtuh.p"]
331    fn vcmpgtuh_p(cr: i32, a: vector_unsigned_short, b: vector_unsigned_short) -> i32;
332    #[link_name = "llvm.ppc.altivec.vcmpgtuw.p"]
333    fn vcmpgtuw_p(cr: i32, a: vector_unsigned_int, b: vector_unsigned_int) -> i32;
334    #[link_name = "llvm.ppc.altivec.vcmpgtsb.p"]
335    fn vcmpgtsb_p(cr: i32, a: vector_signed_char, b: vector_signed_char) -> i32;
336    #[link_name = "llvm.ppc.altivec.vcmpgtsh.p"]
337    fn vcmpgtsh_p(cr: i32, a: vector_signed_short, b: vector_signed_short) -> i32;
338    #[link_name = "llvm.ppc.altivec.vcmpgtsw.p"]
339    fn vcmpgtsw_p(cr: i32, a: vector_signed_int, b: vector_signed_int) -> i32;
340
341    #[link_name = "llvm.ppc.altivec.vcmpgefp.p"]
342    fn vcmpgefp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
343    #[link_name = "llvm.ppc.altivec.vcmpgtfp.p"]
344    fn vcmpgtfp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
345    #[link_name = "llvm.ppc.altivec.vcmpbfp.p"]
346    fn vcmpbfp_p(cr: i32, a: vector_float, b: vector_float) -> i32;
347
348    #[link_name = "llvm.ppc.altivec.vcfsx"]
349    fn vcfsx(a: vector_signed_int, b: i32) -> vector_float;
350    #[link_name = "llvm.ppc.altivec.vcfux"]
351    fn vcfux(a: vector_unsigned_int, b: i32) -> vector_float;
352
353    #[link_name = "llvm.ppc.altivec.vctsxs"]
354    fn vctsxs(a: vector_float, b: i32) -> vector_signed_int;
355    #[link_name = "llvm.ppc.altivec.vctuxs"]
356    fn vctuxs(a: vector_float, b: i32) -> vector_unsigned_int;
357
358    #[link_name = "llvm.ppc.altivec.vpkshss"]
359    fn vpkshss(a: vector_signed_short, b: vector_signed_short) -> vector_signed_char;
360    #[link_name = "llvm.ppc.altivec.vpkshus"]
361    fn vpkshus(a: vector_signed_short, b: vector_signed_short) -> vector_unsigned_char;
362    #[link_name = "llvm.ppc.altivec.vpkuhus"]
363    fn vpkuhus(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_char;
364    #[link_name = "llvm.ppc.altivec.vpkswss"]
365    fn vpkswss(a: vector_signed_int, b: vector_signed_int) -> vector_signed_short;
366    #[link_name = "llvm.ppc.altivec.vpkswus"]
367    fn vpkswus(a: vector_signed_int, b: vector_signed_int) -> vector_unsigned_short;
368    #[link_name = "llvm.ppc.altivec.vpkuwus"]
369    fn vpkuwus(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_short;
370
371    #[link_name = "llvm.ppc.altivec.vupkhsb"]
372    fn vupkhsb(a: vector_signed_char) -> vector_signed_short;
373    #[link_name = "llvm.ppc.altivec.vupklsb"]
374    fn vupklsb(a: vector_signed_char) -> vector_signed_short;
375
376    #[link_name = "llvm.ppc.altivec.vupkhsh"]
377    fn vupkhsh(a: vector_signed_short) -> vector_signed_int;
378    #[link_name = "llvm.ppc.altivec.vupklsh"]
379    fn vupklsh(a: vector_signed_short) -> vector_signed_int;
380
381    #[link_name = "llvm.ppc.altivec.mfvscr"]
382    fn mfvscr() -> vector_unsigned_short;
383
384    #[link_name = "llvm.ppc.altivec.vlogefp"]
385    fn vlogefp(a: vector_float) -> vector_float;
386
387    #[link_name = "llvm.ppc.altivec.vsl"]
388    fn vsl(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
389    #[link_name = "llvm.ppc.altivec.vslo"]
390    fn vslo(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
391
392    #[link_name = "llvm.ppc.altivec.vsrab"]
393    fn vsrab(a: vector_signed_char, b: vector_unsigned_char) -> vector_signed_char;
394    #[link_name = "llvm.ppc.altivec.vsrah"]
395    fn vsrah(a: vector_signed_short, b: vector_unsigned_short) -> vector_signed_short;
396    #[link_name = "llvm.ppc.altivec.vsraw"]
397    fn vsraw(a: vector_signed_int, b: vector_unsigned_int) -> vector_signed_int;
398
399    #[link_name = "llvm.ppc.altivec.vsr"]
400    fn vsr(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
401    #[link_name = "llvm.ppc.altivec.vsro"]
402    fn vsro(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
403
404    #[link_name = "llvm.ppc.altivec.vslv"]
405    fn vslv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
406    #[link_name = "llvm.ppc.altivec.vsrv"]
407    fn vsrv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
408
409    #[link_name = "llvm.nearbyint.v4f32"]
410    fn vrfin(a: vector_float) -> vector_float;
411}
412
413#[macro_use]
414mod sealed {
415    use super::*;
416
417    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
418    pub trait VectorNeg {
419        unsafe fn vec_neg(self) -> Self;
420    }
421
422    macro_rules! impl_neg {
423        ($($v:ty)*) => {
424            $(
425                #[unstable(feature = "stdarch_powerpc", issue = "111145")]
426                impl VectorNeg for $v {
427                    #[inline]
428                    #[target_feature(enable = "altivec")]
429                    unsafe fn vec_neg(self) -> Self {
430                        simd_neg(self)
431                    }
432                }
433            )*
434        }
435    }
436
437    impl_neg! {
438        vector_signed_char
439        vector_unsigned_char
440        vector_bool_char
441
442        vector_signed_short
443        vector_unsigned_short
444        vector_bool_short
445
446        vector_signed_int
447        vector_unsigned_int
448        vector_bool_int
449
450        vector_float
451    }
452
453    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
454    pub trait VectorInsert {
455        type Scalar;
456        unsafe fn vec_insert<const IDX: u32>(self, s: Self::Scalar) -> Self;
457    }
458
459    const fn idx_in_vec<T, const IDX: u32>() -> u32 {
460        IDX & (16 / crate::mem::size_of::<T>() as u32)
461    }
462
463    macro_rules! impl_vec_insert {
464        ($ty:ident) => {
465            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
466            impl VectorInsert for t_t_l!($ty) {
467                type Scalar = $ty;
468                #[inline]
469                #[target_feature(enable = "altivec")]
470                unsafe fn vec_insert<const IDX: u32>(self, s: Self::Scalar) -> Self {
471                    simd_insert(self, const { idx_in_vec::<Self::Scalar, IDX>() }, s)
472                }
473            }
474        };
475    }
476
477    impl_vec_insert! { i8 }
478    impl_vec_insert! { u8 }
479    impl_vec_insert! { i16 }
480    impl_vec_insert! { u16 }
481    impl_vec_insert! { i32 }
482    impl_vec_insert! { u32 }
483    impl_vec_insert! { f32 }
484
485    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
486    pub trait VectorExtract {
487        type Scalar;
488        unsafe fn vec_extract<const IDX: u32>(self) -> Self::Scalar;
489    }
490
491    macro_rules! impl_vec_extract {
492        ($ty:ident) => {
493            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
494            impl VectorExtract for t_t_l!($ty) {
495                type Scalar = $ty;
496                #[inline]
497                #[target_feature(enable = "altivec")]
498                unsafe fn vec_extract<const IDX: u32>(self) -> Self::Scalar {
499                    simd_extract(self, const { idx_in_vec::<Self::Scalar, IDX>() })
500                }
501            }
502        };
503    }
504
505    impl_vec_extract! { i8 }
506    impl_vec_extract! { u8 }
507    impl_vec_extract! { i16 }
508    impl_vec_extract! { u16 }
509    impl_vec_extract! { i32 }
510    impl_vec_extract! { u32 }
511    impl_vec_extract! { f32 }
512
513    macro_rules! impl_vec_cmp {
514        ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
515            impl_vec_cmp! { [$Trait $m] ($b, $b, $h, $h, $w, $w) }
516        };
517        ([$Trait:ident $m:ident] ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
518            impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, vector_unsigned_char) -> vector_bool_char }
519            impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, vector_signed_char) -> vector_bool_char }
520            impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, vector_unsigned_short) -> vector_bool_short }
521            impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, vector_signed_short) -> vector_bool_short }
522            impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, vector_unsigned_int) -> vector_bool_int }
523            impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, vector_signed_int) -> vector_bool_int }
524        }
525    }
526
527    macro_rules! impl_vec_any_all {
528        ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
529            impl_vec_any_all! { [$Trait $m] ($b, $b, $h, $h, $w, $w) }
530        };
531        ([$Trait:ident $m:ident] ($ub:ident, $sb:ident, $uh:ident, $sh:ident, $uw:ident, $sw:ident)) => {
532            impl_vec_trait!{ [$Trait $m] $ub (vector_unsigned_char, vector_unsigned_char) -> bool }
533            impl_vec_trait!{ [$Trait $m] $sb (vector_signed_char, vector_signed_char) -> bool }
534            impl_vec_trait!{ [$Trait $m] $uh (vector_unsigned_short, vector_unsigned_short) -> bool }
535            impl_vec_trait!{ [$Trait $m] $sh (vector_signed_short, vector_signed_short) -> bool }
536            impl_vec_trait!{ [$Trait $m] $uw (vector_unsigned_int, vector_unsigned_int) -> bool }
537            impl_vec_trait!{ [$Trait $m] $sw (vector_signed_int, vector_signed_int) -> bool }
538        }
539    }
540
541    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
542    pub trait VectorLd {
543        type Result;
544        unsafe fn vec_ld(self, off: isize) -> Self::Result;
545        unsafe fn vec_ldl(self, off: isize) -> Self::Result;
546    }
547
548    macro_rules! impl_vec_ld {
549        ($fun:ident $fun_lru:ident $ty:ident) => {
550            #[inline]
551            #[target_feature(enable = "altivec")]
552            #[cfg_attr(test, assert_instr(lvx))]
553            pub unsafe fn $fun(off: isize, p: *const $ty) -> t_t_l!($ty) {
554                let addr = (p as *const i8).offset(off);
555                transmute(lvx(addr))
556            }
557
558            #[inline]
559            #[target_feature(enable = "altivec")]
560            #[cfg_attr(test, assert_instr(lvxl))]
561            pub unsafe fn $fun_lru(off: isize, p: *const $ty) -> t_t_l!($ty) {
562                let addr = (p as *const i8).offset(off);
563                transmute(lvxl(addr))
564            }
565
566            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
567            impl VectorLd for *const $ty {
568                type Result = t_t_l!($ty);
569                #[inline]
570                #[target_feature(enable = "altivec")]
571                unsafe fn vec_ld(self, off: isize) -> Self::Result {
572                    $fun(off, self)
573                }
574                #[inline]
575                #[target_feature(enable = "altivec")]
576                unsafe fn vec_ldl(self, off: isize) -> Self::Result {
577                    $fun_lru(off, self)
578                }
579            }
580        };
581    }
582
583    impl_vec_ld! { vec_ld_u8 vec_ldl_u8 u8 }
584    impl_vec_ld! { vec_ld_i8 vec_ldl_i8 i8 }
585
586    impl_vec_ld! { vec_ld_u16 vec_ldl_u16 u16 }
587    impl_vec_ld! { vec_ld_i16 vec_ldl_i16 i16 }
588
589    impl_vec_ld! { vec_ld_u32 vec_ldl_u32 u32 }
590    impl_vec_ld! { vec_ld_i32 vec_ldl_i32 i32 }
591
592    impl_vec_ld! { vec_ld_f32 vec_ldl_f32 f32 }
593
594    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
595    pub trait VectorLde {
596        type Result;
597        unsafe fn vec_lde(self, a: isize) -> Self::Result;
598    }
599
600    macro_rules! impl_vec_lde {
601        ($fun:ident $instr:ident $ty:ident) => {
602            #[inline]
603            #[target_feature(enable = "altivec")]
604            #[cfg_attr(test, assert_instr($instr))]
605            pub unsafe fn $fun(a: isize, b: *const $ty) -> t_t_l!($ty) {
606                let addr = b.byte_offset(a).cast::<i8>();
607                transmute($instr(addr))
608            }
609
610            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
611            impl VectorLde for *const $ty {
612                type Result = t_t_l!($ty);
613                #[inline]
614                #[target_feature(enable = "altivec")]
615                unsafe fn vec_lde(self, a: isize) -> Self::Result {
616                    $fun(a, self)
617                }
618            }
619        };
620    }
621
622    impl_vec_lde! { vec_lde_u8 lvebx u8 }
623    impl_vec_lde! { vec_lde_i8 lvebx i8 }
624
625    impl_vec_lde! { vec_lde_u16 lvehx u16 }
626    impl_vec_lde! { vec_lde_i16 lvehx i16 }
627
628    impl_vec_lde! { vec_lde_u32 lvewx u32 }
629    impl_vec_lde! { vec_lde_i32 lvewx i32 }
630
631    impl_vec_lde! { vec_lde_f32 lvewx f32 }
632
633    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
634    pub trait VectorSt {
635        type Target;
636        unsafe fn vec_st(self, off: isize, p: Self::Target);
637        unsafe fn vec_stl(self, off: isize, p: Self::Target);
638    }
639
640    macro_rules! impl_vec_st {
641        ($fun:ident $fun_lru:ident $ty:ident) => {
642            #[inline]
643            #[target_feature(enable = "altivec")]
644            #[cfg_attr(test, assert_instr(stvx))]
645            pub unsafe fn $fun(a: t_t_l!($ty), off: isize, p: *const $ty) {
646                let addr = (p as *const i8).offset(off);
647                stvx(transmute(a), addr)
648            }
649
650            #[inline]
651            #[target_feature(enable = "altivec")]
652            #[cfg_attr(test, assert_instr(stvxl))]
653            pub unsafe fn $fun_lru(a: t_t_l!($ty), off: isize, p: *const $ty) {
654                let addr = (p as *const i8).offset(off as isize);
655                stvxl(transmute(a), addr)
656            }
657
658            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
659            impl VectorSt for t_t_l!($ty) {
660                type Target = *const $ty;
661                #[inline]
662                #[target_feature(enable = "altivec")]
663                unsafe fn vec_st(self, off: isize, p: Self::Target) {
664                    $fun(self, off, p)
665                }
666                #[inline]
667                #[target_feature(enable = "altivec")]
668                unsafe fn vec_stl(self, off: isize, p: Self::Target) {
669                    $fun(self, off, p)
670                }
671            }
672        };
673    }
674
675    impl_vec_st! { vec_st_u8 vec_stl_u8 u8 }
676    impl_vec_st! { vec_st_i8 vec_stl_i8 i8 }
677
678    impl_vec_st! { vec_st_u16 vec_stl_u16 u16 }
679    impl_vec_st! { vec_st_i16 vec_stl_i16 i16 }
680
681    impl_vec_st! { vec_st_u32 vec_stl_u32 u32 }
682    impl_vec_st! { vec_st_i32 vec_stl_i32 i32 }
683
684    impl_vec_st! { vec_st_f32 vec_stl_f32 f32 }
685
686    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
687    pub trait VectorSte {
688        type Target;
689        unsafe fn vec_ste(self, off: isize, p: Self::Target);
690    }
691
692    macro_rules! impl_vec_ste {
693        ($fun:ident $instr:ident $ty:ident) => {
694            #[inline]
695            #[target_feature(enable = "altivec")]
696            #[cfg_attr(test, assert_instr($instr))]
697            pub unsafe fn $fun(a: t_t_l!($ty), off: isize, p: *const $ty) {
698                let addr = (p as *const i8).offset(off);
699                $instr(transmute(a), addr)
700            }
701
702            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
703            impl VectorSte for t_t_l!($ty) {
704                type Target = *const $ty;
705                #[inline]
706                #[target_feature(enable = "altivec")]
707                unsafe fn vec_ste(self, off: isize, p: Self::Target) {
708                    $fun(self, off, p)
709                }
710            }
711        };
712    }
713
714    impl_vec_ste! { vec_ste_u8 stvebx u8 }
715    impl_vec_ste! { vec_ste_i8 stvebx i8 }
716
717    impl_vec_ste! { vec_ste_u16 stvehx u16 }
718    impl_vec_ste! { vec_ste_i16 stvehx i16 }
719
720    impl_vec_ste! { vec_ste_u32 stvewx u32 }
721    impl_vec_ste! { vec_ste_i32 stvewx i32 }
722
723    impl_vec_ste! { vec_ste_f32 stvewx f32 }
724
725    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
726    pub trait VectorXl {
727        type Result;
728        unsafe fn vec_xl(self, a: isize) -> Self::Result;
729    }
730
731    macro_rules! impl_vec_xl {
732        ($fun:ident $notpwr9:ident / $pwr9:ident $ty:ident) => {
733            #[inline]
734            #[target_feature(enable = "altivec")]
735            #[cfg_attr(
736                all(test, not(target_feature = "power9-altivec")),
737                assert_instr($notpwr9)
738            )]
739            #[cfg_attr(all(test, target_feature = "power9-altivec"), assert_instr($pwr9))]
740            pub unsafe fn $fun(a: isize, b: *const $ty) -> t_t_l!($ty) {
741                let addr = (b as *const u8).offset(a);
742
743                let mut r = mem::MaybeUninit::uninit();
744
745                crate::ptr::copy_nonoverlapping(
746                    addr,
747                    r.as_mut_ptr() as *mut u8,
748                    mem::size_of::<t_t_l!($ty)>(),
749                );
750
751                r.assume_init()
752            }
753
754            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
755            impl VectorXl for *const $ty {
756                type Result = t_t_l!($ty);
757                #[inline]
758                #[target_feature(enable = "altivec")]
759                unsafe fn vec_xl(self, a: isize) -> Self::Result {
760                    $fun(a, self)
761                }
762            }
763        };
764    }
765
766    impl_vec_xl! { vec_xl_i8 lxvd2x / lxv i8 }
767    impl_vec_xl! { vec_xl_u8 lxvd2x / lxv u8 }
768    impl_vec_xl! { vec_xl_i16 lxvd2x / lxv i16 }
769    impl_vec_xl! { vec_xl_u16 lxvd2x / lxv u16 }
770    impl_vec_xl! { vec_xl_i32 lxvd2x / lxv i32 }
771    impl_vec_xl! { vec_xl_u32 lxvd2x / lxv u32 }
772    impl_vec_xl! { vec_xl_f32 lxvd2x / lxv f32 }
773
774    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
775    pub trait VectorXst {
776        type Out;
777        unsafe fn vec_xst(self, a: isize, p: Self::Out);
778    }
779
780    macro_rules! impl_vec_xst {
781        ($fun:ident $notpwr9:ident / $pwr9:ident $ty:ident) => {
782            #[inline]
783            #[target_feature(enable = "altivec")]
784            #[cfg_attr(
785                all(test, not(target_feature = "power9-altivec")),
786                assert_instr($notpwr9)
787            )]
788            #[cfg_attr(all(test, target_feature = "power9-altivec"), assert_instr($pwr9))]
789            pub unsafe fn $fun(s: t_t_l!($ty), a: isize, b: *mut $ty) {
790                let addr = (b as *mut u8).offset(a);
791
792                crate::ptr::copy_nonoverlapping(
793                    &s as *const _ as *const u8,
794                    addr,
795                    mem::size_of::<t_t_l!($ty)>(),
796                );
797            }
798
799            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
800            impl VectorXst for t_t_l!($ty) {
801                type Out = *mut $ty;
802                #[inline]
803                #[target_feature(enable = "altivec")]
804                unsafe fn vec_xst(self, a: isize, b: Self::Out) {
805                    $fun(self, a, b)
806                }
807            }
808        };
809    }
810
811    impl_vec_xst! { vec_xst_i8 stxvd2x / stxv i8 }
812    impl_vec_xst! { vec_xst_u8 stxvd2x / stxv u8 }
813    impl_vec_xst! { vec_xst_i16 stxvd2x / stxv i16 }
814    impl_vec_xst! { vec_xst_u16 stxvd2x / stxv u16 }
815    impl_vec_xst! { vec_xst_i32 stxvd2x / stxv i32 }
816    impl_vec_xst! { vec_xst_u32 stxvd2x / stxv u32 }
817    impl_vec_xst! { vec_xst_f32 stxvd2x / stxv f32 }
818
819    test_impl! { vec_floor(a: vector_float) -> vector_float [ simd_floor, vrfim / xvrspim ] }
820
821    test_impl! { vec_vexptefp(a: vector_float) -> vector_float [ vexptefp, vexptefp ] }
822
823    test_impl! { vec_vcmpgtub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char [ vcmpgtub, vcmpgtub ] }
824    test_impl! { vec_vcmpgtuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short [ vcmpgtuh, vcmpgtuh ] }
825    test_impl! { vec_vcmpgtuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int [ vcmpgtuw, vcmpgtuw ] }
826
827    test_impl! { vec_vcmpgtsb(a: vector_signed_char, b: vector_signed_char) -> vector_bool_char [ vcmpgtsb, vcmpgtsb ] }
828    test_impl! { vec_vcmpgtsh(a: vector_signed_short, b: vector_signed_short) -> vector_bool_short [ vcmpgtsh, vcmpgtsh ] }
829    test_impl! { vec_vcmpgtsw(a: vector_signed_int, b: vector_signed_int) -> vector_bool_int [ vcmpgtsw, vcmpgtsw ] }
830
831    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
832    pub trait VectorCmpGt<Other> {
833        type Result;
834        unsafe fn vec_cmpgt(self, b: Other) -> Self::Result;
835    }
836
837    impl_vec_cmp! { [VectorCmpGt vec_cmpgt] ( vec_vcmpgtub, vec_vcmpgtsb, vec_vcmpgtuh, vec_vcmpgtsh, vec_vcmpgtuw, vec_vcmpgtsw ) }
838
839    test_impl! { vec_vcmpgefp(a: vector_float, b: vector_float) -> vector_bool_int [ vcmpgefp, vcmpgefp ] }
840
841    test_impl! { vec_vcmpequb(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_bool_char [ vcmpequb, vcmpequb ] }
842    test_impl! { vec_vcmpequh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_bool_short [ vcmpequh, vcmpequh ] }
843    test_impl! { vec_vcmpequw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_bool_int [ vcmpequw, vcmpequw ] }
844
845    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
846    pub trait VectorCmpEq<Other> {
847        type Result;
848        unsafe fn vec_cmpeq(self, b: Other) -> Self::Result;
849    }
850
851    impl_vec_cmp! { [VectorCmpEq vec_cmpeq] (vec_vcmpequb, vec_vcmpequh, vec_vcmpequw) }
852
853    macro_rules! impl_cmpne {
854        ($fun:ident ($ty:ident) -> $r:ident $([ $pwr9:ident ])? ) => {
855            #[inline]
856            #[target_feature(enable = "altivec")]
857            $( #[cfg_attr(all(test, target_feature = "power9-altivec"), assert_instr($pwr9))] )?
858            unsafe fn $fun(a: $ty, b: $ty) -> $r {
859                $( if cfg!(target_feature = "power9-altivec") {
860                    transmute($pwr9(transmute(a), transmute(b)))
861                } else )? {
862                    let zero = transmute(i32x4::new(0, 0, 0, 0));
863                    vec_nor(vec_cmpeq(a, b), zero)
864                }
865            }
866        };
867    }
868
869    impl_cmpne! { vec_vcmpneb(vector_signed_char) -> vector_bool_char [ vcmpneb ] }
870    impl_cmpne! { vec_vcmpneh(vector_signed_short) -> vector_bool_short [ vcmpneh ] }
871    impl_cmpne! { vec_vcmpnew(vector_signed_int) -> vector_bool_int [ vcmpnew ] }
872
873    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
874    pub trait VectorCmpNe<Other> {
875        type Result;
876        unsafe fn vec_cmpne(self, b: Other) -> Self::Result;
877    }
878
879    impl_vec_cmp! { [VectorCmpNe vec_cmpne] (vec_vcmpneb, vec_vcmpneh, vec_vcmpnew) }
880
881    test_impl! { vec_vcmpbfp(a: vector_float, b: vector_float) -> vector_signed_int [vcmpbfp, vcmpbfp] }
882
883    #[inline]
884    #[target_feature(enable = "altivec")]
885    #[cfg_attr(test, assert_instr(vcmpequb.))]
886    unsafe fn vcmpequb_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
887        vcmpequb_p(2, a, b) != 0
888    }
889
890    #[inline]
891    #[target_feature(enable = "altivec")]
892    #[cfg_attr(test, assert_instr(vcmpequb.))]
893    unsafe fn vcmpequb_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
894        vcmpequb_p(1, a, b) != 0
895    }
896
897    #[inline]
898    #[target_feature(enable = "altivec")]
899    #[cfg_attr(test, assert_instr(vcmpequh.))]
900    unsafe fn vcmpequh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
901        vcmpequh_p(2, a, b) != 0
902    }
903
904    #[inline]
905    #[target_feature(enable = "altivec")]
906    #[cfg_attr(test, assert_instr(vcmpequh.))]
907    unsafe fn vcmpequh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
908        vcmpequh_p(1, a, b) != 0
909    }
910
911    #[inline]
912    #[target_feature(enable = "altivec")]
913    #[cfg_attr(test, assert_instr(vcmpequw.))]
914    unsafe fn vcmpequw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
915        vcmpequw_p(2, a, b) != 0
916    }
917
918    #[inline]
919    #[target_feature(enable = "altivec")]
920    #[cfg_attr(test, assert_instr(vcmpequw.))]
921    unsafe fn vcmpequw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
922        vcmpequw_p(1, a, b) != 0
923    }
924
925    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
926    pub trait VectorAllEq<Other> {
927        type Result;
928        unsafe fn vec_all_eq(self, b: Other) -> Self::Result;
929    }
930
931    impl_vec_any_all! { [VectorAllEq vec_all_eq] (vcmpequb_all, vcmpequh_all, vcmpequw_all) }
932
933    // TODO: vsx encoding
934    #[inline]
935    #[target_feature(enable = "altivec")]
936    #[cfg_attr(test, assert_instr(vcmpeqfp.))]
937    unsafe fn vcmpeqfp_all(a: vector_float, b: vector_float) -> bool {
938        vcmpeqfp_p(2, a, b) != 0
939    }
940
941    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
942    impl VectorAllEq<vector_float> for vector_float {
943        type Result = bool;
944        #[inline]
945        unsafe fn vec_all_eq(self, b: vector_float) -> Self::Result {
946            vcmpeqfp_all(self, b)
947        }
948    }
949
950    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
951    pub trait VectorAnyEq<Other> {
952        type Result;
953        unsafe fn vec_any_eq(self, b: Other) -> Self::Result;
954    }
955
956    impl_vec_any_all! { [VectorAnyEq vec_any_eq] (vcmpequb_any, vcmpequh_any, vcmpequw_any) }
957
958    #[inline]
959    #[target_feature(enable = "altivec")]
960    #[cfg_attr(test, assert_instr(vcmpeqfp.))]
961    unsafe fn vcmpeqfp_any(a: vector_float, b: vector_float) -> bool {
962        vcmpeqfp_p(1, a, b) != 0
963    }
964
965    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
966    impl VectorAnyEq<vector_float> for vector_float {
967        type Result = bool;
968        #[inline]
969        unsafe fn vec_any_eq(self, b: vector_float) -> Self::Result {
970            vcmpeqfp_any(self, b)
971        }
972    }
973
974    // All/Any GreaterEqual
975
976    #[inline]
977    #[target_feature(enable = "altivec")]
978    #[cfg_attr(test, assert_instr(vcmpgtsb.))]
979    unsafe fn vcmpgesb_all(a: vector_signed_char, b: vector_signed_char) -> bool {
980        vcmpgtsb_p(0, b, a) != 0
981    }
982
983    #[inline]
984    #[target_feature(enable = "altivec")]
985    #[cfg_attr(test, assert_instr(vcmpgtsb.))]
986    unsafe fn vcmpgesb_any(a: vector_signed_char, b: vector_signed_char) -> bool {
987        vcmpgtsb_p(3, b, a) != 0
988    }
989
990    #[inline]
991    #[target_feature(enable = "altivec")]
992    #[cfg_attr(test, assert_instr(vcmpgtsh.))]
993    unsafe fn vcmpgesh_all(a: vector_signed_short, b: vector_signed_short) -> bool {
994        vcmpgtsh_p(0, b, a) != 0
995    }
996
997    #[inline]
998    #[target_feature(enable = "altivec")]
999    #[cfg_attr(test, assert_instr(vcmpgtsh.))]
1000    unsafe fn vcmpgesh_any(a: vector_signed_short, b: vector_signed_short) -> bool {
1001        vcmpgtsh_p(3, b, a) != 0
1002    }
1003
1004    #[inline]
1005    #[target_feature(enable = "altivec")]
1006    #[cfg_attr(test, assert_instr(vcmpgtsw.))]
1007    unsafe fn vcmpgesw_all(a: vector_signed_int, b: vector_signed_int) -> bool {
1008        vcmpgtsw_p(0, b, a) != 0
1009    }
1010
1011    #[inline]
1012    #[target_feature(enable = "altivec")]
1013    #[cfg_attr(test, assert_instr(vcmpgtsw.))]
1014    unsafe fn vcmpgesw_any(a: vector_signed_int, b: vector_signed_int) -> bool {
1015        vcmpgtsw_p(3, b, a) != 0
1016    }
1017
1018    #[inline]
1019    #[target_feature(enable = "altivec")]
1020    #[cfg_attr(test, assert_instr(vcmpgtub.))]
1021    unsafe fn vcmpgeub_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1022        vcmpgtub_p(0, b, a) != 0
1023    }
1024
1025    #[inline]
1026    #[target_feature(enable = "altivec")]
1027    #[cfg_attr(test, assert_instr(vcmpgtub.))]
1028    unsafe fn vcmpgeub_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1029        vcmpgtub_p(3, b, a) != 0
1030    }
1031
1032    #[inline]
1033    #[target_feature(enable = "altivec")]
1034    #[cfg_attr(test, assert_instr(vcmpgtuh.))]
1035    unsafe fn vcmpgeuh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1036        vcmpgtuh_p(0, b, a) != 0
1037    }
1038
1039    #[inline]
1040    #[target_feature(enable = "altivec")]
1041    #[cfg_attr(test, assert_instr(vcmpgtuh.))]
1042    unsafe fn vcmpgeuh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1043        vcmpgtuh_p(3, b, a) != 0
1044    }
1045
1046    #[inline]
1047    #[target_feature(enable = "altivec")]
1048    #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1049    unsafe fn vcmpgeuw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1050        vcmpgtuw_p(0, b, a) != 0
1051    }
1052
1053    #[inline]
1054    #[target_feature(enable = "altivec")]
1055    #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1056    unsafe fn vcmpgeuw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1057        vcmpgtuw_p(3, b, a) != 0
1058    }
1059
1060    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1061    pub trait VectorAllGe<Other> {
1062        type Result;
1063        unsafe fn vec_all_ge(self, b: Other) -> Self::Result;
1064    }
1065
1066    impl_vec_any_all! { [VectorAllGe vec_all_ge] (
1067        vcmpgeub_all, vcmpgesb_all,
1068        vcmpgeuh_all, vcmpgesh_all,
1069        vcmpgeuw_all, vcmpgesw_all
1070    ) }
1071
1072    // TODO: vsx encoding
1073    #[inline]
1074    #[target_feature(enable = "altivec")]
1075    #[cfg_attr(test, assert_instr(vcmpgefp.))]
1076    unsafe fn vcmpgefp_all(a: vector_float, b: vector_float) -> bool {
1077        vcmpgefp_p(2, a, b) != 0
1078    }
1079
1080    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1081    impl VectorAllGe<vector_float> for vector_float {
1082        type Result = bool;
1083        #[inline]
1084        unsafe fn vec_all_ge(self, b: vector_float) -> Self::Result {
1085            vcmpgefp_all(self, b)
1086        }
1087    }
1088
1089    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1090    pub trait VectorAnyGe<Other> {
1091        type Result;
1092        unsafe fn vec_any_ge(self, b: Other) -> Self::Result;
1093    }
1094
1095    impl_vec_any_all! { [VectorAnyGe vec_any_ge] (
1096        vcmpgeub_any, vcmpgesb_any,
1097        vcmpgeuh_any, vcmpgesh_any,
1098        vcmpgeuw_any, vcmpgesw_any
1099    ) }
1100
1101    #[inline]
1102    #[target_feature(enable = "altivec")]
1103    #[cfg_attr(test, assert_instr(vcmpgefp.))]
1104    unsafe fn vcmpgefp_any(a: vector_float, b: vector_float) -> bool {
1105        vcmpgefp_p(1, a, b) != 0
1106    }
1107
1108    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1109    impl VectorAnyGe<vector_float> for vector_float {
1110        type Result = bool;
1111        #[inline]
1112        unsafe fn vec_any_ge(self, b: vector_float) -> Self::Result {
1113            vcmpgefp_any(self, b)
1114        }
1115    }
1116
1117    // All/Any Greater Than
1118
1119    #[inline]
1120    #[target_feature(enable = "altivec")]
1121    #[cfg_attr(test, assert_instr(vcmpgtsb.))]
1122    unsafe fn vcmpgtsb_all(a: vector_signed_char, b: vector_signed_char) -> bool {
1123        vcmpgtsb_p(2, a, b) != 0
1124    }
1125
1126    #[inline]
1127    #[target_feature(enable = "altivec")]
1128    #[cfg_attr(test, assert_instr(vcmpgtsb.))]
1129    unsafe fn vcmpgtsb_any(a: vector_signed_char, b: vector_signed_char) -> bool {
1130        vcmpgtsb_p(1, a, b) != 0
1131    }
1132
1133    #[inline]
1134    #[target_feature(enable = "altivec")]
1135    #[cfg_attr(test, assert_instr(vcmpgtsh.))]
1136    unsafe fn vcmpgtsh_all(a: vector_signed_short, b: vector_signed_short) -> bool {
1137        vcmpgtsh_p(2, a, b) != 0
1138    }
1139
1140    #[inline]
1141    #[target_feature(enable = "altivec")]
1142    #[cfg_attr(test, assert_instr(vcmpgtsh.))]
1143    unsafe fn vcmpgtsh_any(a: vector_signed_short, b: vector_signed_short) -> bool {
1144        vcmpgtsh_p(1, a, b) != 0
1145    }
1146
1147    #[inline]
1148    #[target_feature(enable = "altivec")]
1149    #[cfg_attr(test, assert_instr(vcmpgtsw.))]
1150    unsafe fn vcmpgtsw_all(a: vector_signed_int, b: vector_signed_int) -> bool {
1151        vcmpgtsw_p(2, a, b) != 0
1152    }
1153
1154    #[inline]
1155    #[target_feature(enable = "altivec")]
1156    #[cfg_attr(test, assert_instr(vcmpgtsw.))]
1157    unsafe fn vcmpgtsw_any(a: vector_signed_int, b: vector_signed_int) -> bool {
1158        vcmpgtsw_p(1, a, b) != 0
1159    }
1160
1161    #[inline]
1162    #[target_feature(enable = "altivec")]
1163    #[cfg_attr(test, assert_instr(vcmpgtub.))]
1164    unsafe fn vcmpgtub_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1165        vcmpgtub_p(2, a, b) != 0
1166    }
1167
1168    #[inline]
1169    #[target_feature(enable = "altivec")]
1170    #[cfg_attr(test, assert_instr(vcmpgtub.))]
1171    unsafe fn vcmpgtub_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1172        vcmpgtub_p(1, a, b) != 0
1173    }
1174
1175    #[inline]
1176    #[target_feature(enable = "altivec")]
1177    #[cfg_attr(test, assert_instr(vcmpgtuh.))]
1178    unsafe fn vcmpgtuh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1179        vcmpgtuh_p(2, a, b) != 0
1180    }
1181
1182    #[inline]
1183    #[target_feature(enable = "altivec")]
1184    #[cfg_attr(test, assert_instr(vcmpgtuh.))]
1185    unsafe fn vcmpgtuh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1186        vcmpgtuh_p(1, a, b) != 0
1187    }
1188
1189    #[inline]
1190    #[target_feature(enable = "altivec")]
1191    #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1192    unsafe fn vcmpgtuw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1193        vcmpgtuw_p(2, a, b) != 0
1194    }
1195
1196    #[inline]
1197    #[target_feature(enable = "altivec")]
1198    #[cfg_attr(test, assert_instr(vcmpgtuw.))]
1199    unsafe fn vcmpgtuw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1200        vcmpgtuw_p(1, a, b) != 0
1201    }
1202
1203    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1204    pub trait VectorAllGt<Other> {
1205        type Result;
1206        unsafe fn vec_all_gt(self, b: Other) -> Self::Result;
1207    }
1208
1209    impl_vec_any_all! { [VectorAllGt vec_all_gt] (
1210        vcmpgtub_all, vcmpgtsb_all,
1211        vcmpgtuh_all, vcmpgtsh_all,
1212        vcmpgtuw_all, vcmpgtsw_all
1213    ) }
1214
1215    // TODO: vsx encoding
1216    #[inline]
1217    #[target_feature(enable = "altivec")]
1218    #[cfg_attr(test, assert_instr(vcmpgtfp.))]
1219    unsafe fn vcmpgtfp_all(a: vector_float, b: vector_float) -> bool {
1220        vcmpgtfp_p(2, a, b) != 0
1221    }
1222
1223    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1224    impl VectorAllGt<vector_float> for vector_float {
1225        type Result = bool;
1226        #[inline]
1227        unsafe fn vec_all_gt(self, b: vector_float) -> Self::Result {
1228            vcmpgtfp_all(self, b)
1229        }
1230    }
1231
1232    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1233    pub trait VectorAnyGt<Other> {
1234        type Result;
1235        unsafe fn vec_any_gt(self, b: Other) -> Self::Result;
1236    }
1237
1238    impl_vec_any_all! { [VectorAnyGt vec_any_gt] (
1239        vcmpgtub_any, vcmpgtsb_any,
1240        vcmpgtuh_any, vcmpgtsh_any,
1241        vcmpgtuw_any, vcmpgtsw_any
1242    ) }
1243
1244    #[inline]
1245    #[target_feature(enable = "altivec")]
1246    #[cfg_attr(test, assert_instr(vcmpgtfp.))]
1247    unsafe fn vcmpgtfp_any(a: vector_float, b: vector_float) -> bool {
1248        vcmpgtfp_p(1, a, b) != 0
1249    }
1250
1251    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1252    impl VectorAnyGt<vector_float> for vector_float {
1253        type Result = bool;
1254        #[inline]
1255        unsafe fn vec_any_gt(self, b: vector_float) -> Self::Result {
1256            vcmpgtfp_any(self, b)
1257        }
1258    }
1259
1260    // All/Any Elements Not Equal
1261
1262    #[inline]
1263    #[target_feature(enable = "altivec")]
1264    #[cfg_attr(test, assert_instr(vcmpequb.))]
1265    unsafe fn vcmpneub_all(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1266        vcmpequb_p(0, a, b) != 0
1267    }
1268
1269    #[inline]
1270    #[target_feature(enable = "altivec")]
1271    #[cfg_attr(test, assert_instr(vcmpequb.))]
1272    unsafe fn vcmpneub_any(a: vector_unsigned_char, b: vector_unsigned_char) -> bool {
1273        vcmpequb_p(3, a, b) != 0
1274    }
1275
1276    #[inline]
1277    #[target_feature(enable = "altivec")]
1278    #[cfg_attr(test, assert_instr(vcmpequh.))]
1279    unsafe fn vcmpneuh_all(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1280        vcmpequh_p(0, a, b) != 0
1281    }
1282
1283    #[inline]
1284    #[target_feature(enable = "altivec")]
1285    #[cfg_attr(test, assert_instr(vcmpequh.))]
1286    unsafe fn vcmpneuh_any(a: vector_unsigned_short, b: vector_unsigned_short) -> bool {
1287        vcmpequh_p(3, a, b) != 0
1288    }
1289
1290    #[inline]
1291    #[target_feature(enable = "altivec")]
1292    #[cfg_attr(test, assert_instr(vcmpequw.))]
1293    unsafe fn vcmpneuw_all(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1294        vcmpequw_p(0, a, b) != 0
1295    }
1296
1297    #[inline]
1298    #[target_feature(enable = "altivec")]
1299    #[cfg_attr(test, assert_instr(vcmpequw.))]
1300    unsafe fn vcmpneuw_any(a: vector_unsigned_int, b: vector_unsigned_int) -> bool {
1301        vcmpequw_p(3, a, b) != 0
1302    }
1303
1304    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1305    pub trait VectorAllNe<Other> {
1306        type Result;
1307        unsafe fn vec_all_ne(self, b: Other) -> Self::Result;
1308    }
1309
1310    impl_vec_any_all! { [VectorAllNe vec_all_ne] (vcmpneub_all, vcmpneuh_all, vcmpneuw_all) }
1311
1312    // TODO: vsx encoding
1313    #[inline]
1314    #[target_feature(enable = "altivec")]
1315    #[cfg_attr(test, assert_instr(vcmpeqfp.))]
1316    unsafe fn vcmpnefp_all(a: vector_float, b: vector_float) -> bool {
1317        vcmpeqfp_p(0, a, b) != 0
1318    }
1319
1320    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1321    impl VectorAllNe<vector_float> for vector_float {
1322        type Result = bool;
1323        #[inline]
1324        unsafe fn vec_all_ne(self, b: vector_float) -> Self::Result {
1325            vcmpnefp_all(self, b)
1326        }
1327    }
1328
1329    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1330    pub trait VectorAnyNe<Other> {
1331        type Result;
1332        unsafe fn vec_any_ne(self, b: Other) -> Self::Result;
1333    }
1334
1335    impl_vec_any_all! { [VectorAnyNe vec_any_ne] (vcmpneub_any, vcmpneuh_any, vcmpneuw_any) }
1336
1337    #[inline]
1338    #[target_feature(enable = "altivec")]
1339    #[cfg_attr(test, assert_instr(vcmpeqfp.))]
1340    unsafe fn vcmpnefp_any(a: vector_float, b: vector_float) -> bool {
1341        vcmpeqfp_p(3, a, b) != 0
1342    }
1343
1344    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1345    impl VectorAnyNe<vector_float> for vector_float {
1346        type Result = bool;
1347        #[inline]
1348        unsafe fn vec_any_ne(self, b: vector_float) -> Self::Result {
1349            vcmpnefp_any(self, b)
1350        }
1351    }
1352
1353    test_impl! { vec_vceil(a: vector_float) -> vector_float [simd_ceil, vrfip / xvrspip ] }
1354
1355    test_impl! { vec_vavgsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vavgsb, vavgsb ] }
1356    test_impl! { vec_vavgsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vavgsh, vavgsh ] }
1357    test_impl! { vec_vavgsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vavgsw, vavgsw ] }
1358    test_impl! { vec_vavgub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vavgub, vavgub ] }
1359    test_impl! { vec_vavguh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vavguh, vavguh ] }
1360    test_impl! { vec_vavguw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vavguw, vavguw ] }
1361
1362    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1363    pub trait VectorAvg<Other> {
1364        type Result;
1365        unsafe fn vec_avg(self, b: Other) -> Self::Result;
1366    }
1367
1368    impl_vec_trait! { [VectorAvg vec_avg] 2 (vec_vavgub, vec_vavgsb, vec_vavguh, vec_vavgsh, vec_vavguw, vec_vavgsw) }
1369
1370    #[inline]
1371    #[target_feature(enable = "altivec")]
1372    #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vandc))]
1373    #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlandc))]
1374    unsafe fn andc(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
1375        let a = transmute(a);
1376        let b = transmute(b);
1377        transmute(simd_and(simd_xor(u8x16::splat(0xff), b), a))
1378    }
1379
1380    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1381    pub trait VectorAndc<Other> {
1382        type Result;
1383        unsafe fn vec_andc(self, b: Other) -> Self::Result;
1384    }
1385
1386    impl_vec_trait! { [VectorAndc vec_andc]+ 2b (andc) }
1387
1388    #[inline]
1389    #[target_feature(enable = "altivec")]
1390    #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vorc))]
1391    #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlorc))]
1392    unsafe fn orc(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
1393        let a = transmute(a);
1394        let b = transmute(b);
1395        transmute(simd_or(simd_xor(u8x16::splat(0xff), b), a))
1396    }
1397
1398    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1399    pub trait VectorOrc<Other> {
1400        type Result;
1401        unsafe fn vec_orc(self, b: Other) -> Self::Result;
1402    }
1403
1404    impl_vec_trait! { [VectorOrc vec_orc]+ 2b (orc) }
1405
1406    test_impl! { vec_vand(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ simd_and, vand / xxland ] }
1407
1408    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1409    pub trait VectorAnd<Other> {
1410        type Result;
1411        unsafe fn vec_and(self, b: Other) -> Self::Result;
1412    }
1413
1414    impl_vec_trait! { [VectorAnd vec_and] ~(simd_and) }
1415
1416    test_impl! { vec_vaddsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vaddsbs, vaddsbs ] }
1417    test_impl! { vec_vaddshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vaddshs, vaddshs ] }
1418    test_impl! { vec_vaddsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vaddsws, vaddsws ] }
1419    test_impl! { vec_vaddubs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vaddubs, vaddubs ] }
1420    test_impl! { vec_vadduhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vadduhs, vadduhs ] }
1421    test_impl! { vec_vadduws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vadduws, vadduws ] }
1422
1423    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1424    pub trait VectorAdds<Other> {
1425        type Result;
1426        unsafe fn vec_adds(self, b: Other) -> Self::Result;
1427    }
1428
1429    impl_vec_trait! { [VectorAdds vec_adds] ~(vaddubs, vaddsbs, vadduhs, vaddshs, vadduws, vaddsws) }
1430
1431    test_impl! { vec_vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vaddcuw, vaddcuw] }
1432
1433    test_impl! { vec_vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vsubsbs, vsubsbs ] }
1434    test_impl! { vec_vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vsubshs, vsubshs ] }
1435    test_impl! { vec_vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vsubsws, vsubsws ] }
1436    test_impl! { vec_vsububs(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [ vsububs, vsububs ] }
1437    test_impl! { vec_vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [ vsubuhs, vsubuhs ] }
1438    test_impl! { vec_vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vsubuws, vsubuws ] }
1439
1440    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1441    pub trait VectorSubs<Other> {
1442        type Result;
1443        unsafe fn vec_subs(self, b: Other) -> Self::Result;
1444    }
1445
1446    impl_vec_trait! { [VectorSubs vec_subs] ~(vsububs, vsubsbs, vsubuhs, vsubshs, vsubuws, vsubsws) }
1447
1448    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1449    pub trait VectorAbs {
1450        unsafe fn vec_abs(self) -> Self;
1451    }
1452
1453    macro_rules! impl_abs {
1454        ($name:ident,  $ty: ident) => {
1455            #[inline]
1456            #[target_feature(enable = "altivec")]
1457            unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
1458                v.vec_max(simd_neg(v))
1459            }
1460
1461            impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
1462        };
1463    }
1464
1465    impl_abs! { vec_abs_i8, i8x16 }
1466    impl_abs! { vec_abs_i16, i16x8 }
1467    impl_abs! { vec_abs_i32, i32x4 }
1468
1469    #[inline]
1470    #[target_feature(enable = "altivec")]
1471    unsafe fn vec_abs_f32(v: vector_float) -> vector_float {
1472        let v: u32x4 = transmute(v);
1473
1474        transmute(simd_and(v, u32x4::splat(0x7FFFFFFF)))
1475    }
1476
1477    impl_vec_trait! { [VectorAbs vec_abs] vec_abs_f32 (vector_float) }
1478
1479    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1480    pub trait VectorAbss {
1481        unsafe fn vec_abss(self) -> Self;
1482    }
1483
1484    macro_rules! impl_abss {
1485        ($name:ident,  $ty: ident) => {
1486            #[inline]
1487            #[target_feature(enable = "altivec")]
1488            unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
1489                let zero: s_t_l!($ty) = transmute(0u8.vec_splats());
1490                v.vec_max(zero.vec_subs(v))
1491            }
1492
1493            impl_vec_trait! { [VectorAbss vec_abss] $name (s_t_l!($ty)) }
1494        };
1495    }
1496
1497    impl_abss! { vec_abss_i8, i8x16 }
1498    impl_abss! { vec_abss_i16, i16x8 }
1499    impl_abss! { vec_abss_i32, i32x4 }
1500
1501    #[inline]
1502    #[target_feature(enable = "altivec")]
1503    #[cfg_attr(test, assert_instr(vspltb, IMM4 = 15))]
1504    unsafe fn vspltb<const IMM4: u32>(a: vector_signed_char) -> vector_signed_char {
1505        static_assert_uimm_bits!(IMM4, 4);
1506        simd_shuffle(a, a, const { u32x16::splat(IMM4) })
1507    }
1508
1509    #[inline]
1510    #[target_feature(enable = "altivec")]
1511    #[cfg_attr(test, assert_instr(vsplth, IMM3 = 7))]
1512    unsafe fn vsplth<const IMM3: u32>(a: vector_signed_short) -> vector_signed_short {
1513        static_assert_uimm_bits!(IMM3, 3);
1514        simd_shuffle(a, a, const { u32x8::splat(IMM3) })
1515    }
1516
1517    #[inline]
1518    #[target_feature(enable = "altivec")]
1519    #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vspltw, IMM2 = 3))]
1520    #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxspltw, IMM2 = 3))]
1521    unsafe fn vspltw<const IMM2: u32>(a: vector_signed_int) -> vector_signed_int {
1522        static_assert_uimm_bits!(IMM2, 2);
1523        simd_shuffle(a, a, const { u32x4::splat(IMM2) })
1524    }
1525
1526    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1527    pub trait VectorSplat {
1528        unsafe fn vec_splat<const IMM: u32>(self) -> Self;
1529    }
1530
1531    macro_rules! impl_vec_splat {
1532        ($ty:ty, $fun:ident) => {
1533            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1534            impl VectorSplat for $ty {
1535                #[inline]
1536                #[target_feature(enable = "altivec")]
1537                unsafe fn vec_splat<const IMM: u32>(self) -> Self {
1538                    transmute($fun::<IMM>(transmute(self)))
1539                }
1540            }
1541        };
1542    }
1543
1544    impl_vec_splat! { vector_signed_char, vspltb }
1545    impl_vec_splat! { vector_unsigned_char, vspltb }
1546    impl_vec_splat! { vector_bool_char, vspltb }
1547    impl_vec_splat! { vector_signed_short, vsplth }
1548    impl_vec_splat! { vector_unsigned_short, vsplth }
1549    impl_vec_splat! { vector_bool_short, vsplth }
1550    impl_vec_splat! { vector_signed_int, vspltw }
1551    impl_vec_splat! { vector_unsigned_int, vspltw }
1552    impl_vec_splat! { vector_bool_int, vspltw }
1553
1554    macro_rules! splat {
1555        ($name:ident, $v:ident, $r:ident [$instr_altivec:ident / $instr_pwr9:ident, $doc:literal]) => {
1556            #[doc = $doc]
1557            #[inline]
1558            #[target_feature(enable = "altivec")]
1559            #[cfg_attr(
1560                all(test, not(target_feature = "vsx")),
1561                assert_instr($instr_altivec, IMM5 = 1)
1562            )]
1563            #[cfg_attr(
1564                all(test, target_feature = "power9-vector"),
1565                assert_instr($instr_pwr9, IMM5 = 1)
1566            )]
1567            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1568            pub unsafe fn $name<const IMM5: i8>() -> s_t_l!($r) {
1569                static_assert_simm_bits!(IMM5, 5);
1570                transmute($r::splat(IMM5 as $v))
1571            }
1572        };
1573        ($name:ident, $v:ident, $r:ident [$instr:ident, $doc:literal]) => {
1574            splat! { $name, $v, $r [$instr / $instr, $doc] }
1575        };
1576    }
1577
1578    macro_rules! splats {
1579        ($name:ident, $v:ident, $r:ident) => {
1580            #[inline]
1581            #[target_feature(enable = "altivec")]
1582            unsafe fn $name(v: $v) -> s_t_l!($r) {
1583                transmute($r::splat(v))
1584            }
1585        };
1586    }
1587
1588    splats! { splats_u8, u8, u8x16 }
1589    splats! { splats_u16, u16, u16x8 }
1590    splats! { splats_u32, u32, u32x4 }
1591    splats! { splats_i8, i8, i8x16 }
1592    splats! { splats_i16, i16, i16x8 }
1593    splats! { splats_i32, i32, i32x4 }
1594    splats! { splats_f32, f32, f32x4 }
1595
1596    test_impl! { vec_splats_u8 (v: u8) -> vector_unsigned_char [splats_u8, vspltb] }
1597    test_impl! { vec_splats_u16 (v: u16) -> vector_unsigned_short [splats_u16, vsplth] }
1598    test_impl! { vec_splats_u32 (v: u32) -> vector_unsigned_int [splats_u32, vspltw / xxspltw / mtvsrws] }
1599    test_impl! { vec_splats_i8 (v: i8) -> vector_signed_char [splats_i8, vspltb] }
1600    test_impl! { vec_splats_i16 (v: i16) -> vector_signed_short [splats_i16, vsplth] }
1601    test_impl! { vec_splats_i32 (v: i32) -> vector_signed_int [splats_i32, vspltw / xxspltw / mtvsrws] }
1602    test_impl! { vec_splats_f32 (v: f32) -> vector_float [splats_f32, vspltw / xxspltw / mtvsrws] }
1603
1604    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1605    pub trait VectorSplats {
1606        type Result;
1607        unsafe fn vec_splats(self) -> Self::Result;
1608    }
1609
1610    macro_rules! impl_vec_splats {
1611        ($(($fn:ident ($ty:ty) -> $r:ty)),*) => {
1612            $(
1613                impl_vec_trait!{ [VectorSplats vec_splats] $fn ($ty) -> $r }
1614            )*
1615        }
1616    }
1617
1618    impl_vec_splats! {
1619        (vec_splats_u8 (u8) -> vector_unsigned_char),
1620        (vec_splats_i8 (i8) -> vector_signed_char),
1621        (vec_splats_u16 (u16) -> vector_unsigned_short),
1622        (vec_splats_i16 (i16) -> vector_signed_short),
1623        (vec_splats_u32 (u32) -> vector_unsigned_int),
1624        (vec_splats_i32 (i32) -> vector_signed_int),
1625        (vec_splats_f32 (f32) -> vector_float)
1626    }
1627
1628    test_impl! { vec_vsububm (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [simd_sub, vsububm] }
1629    test_impl! { vec_vsubuhm (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [simd_sub, vsubuhm] }
1630    test_impl! { vec_vsubuwm (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [simd_sub, vsubuwm] }
1631
1632    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1633    pub trait VectorSub<Other> {
1634        type Result;
1635        unsafe fn vec_sub(self, b: Other) -> Self::Result;
1636    }
1637
1638    impl_vec_trait! { [VectorSub vec_sub] ~(simd_sub, simd_sub, simd_sub, simd_sub, simd_sub, simd_sub) }
1639    impl_vec_trait! { [VectorSub vec_sub] simd_sub(vector_float, vector_float) -> vector_float }
1640
1641    test_impl! { vec_vsubcuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vsubcuw, vsubcuw] }
1642
1643    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1644    pub trait VectorSubc<Other> {
1645        type Result;
1646        unsafe fn vec_subc(self, b: Other) -> Self::Result;
1647    }
1648
1649    impl_vec_trait! {[VectorSubc vec_subc]+ vec_vsubcuw(vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_int }
1650    impl_vec_trait! {[VectorSubc vec_subc]+ vec_vsubcuw(vector_signed_int, vector_signed_int) -> vector_signed_int }
1651
1652    test_impl! { vec_vminsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vminsb, vminsb] }
1653    test_impl! { vec_vminsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vminsh, vminsh] }
1654    test_impl! { vec_vminsw (a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [vminsw, vminsw] }
1655
1656    test_impl! { vec_vminub (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [vminub, vminub] }
1657    test_impl! { vec_vminuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vminuh, vminuh] }
1658    test_impl! { vec_vminuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vminuw, vminuw] }
1659
1660    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1661    pub trait VectorMin<Other> {
1662        type Result;
1663        unsafe fn vec_min(self, b: Other) -> Self::Result;
1664    }
1665
1666    impl_vec_trait! { [VectorMin vec_min] ~(vminub, vminsb, vminuh, vminsh, vminuw, vminsw) }
1667
1668    test_impl! { vec_vmaxsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vmaxsb, vmaxsb] }
1669    test_impl! { vec_vmaxsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vmaxsh, vmaxsh] }
1670    test_impl! { vec_vmaxsw (a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [vmaxsw, vmaxsw] }
1671
1672    test_impl! { vec_vmaxub (a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char [vmaxub, vmaxub] }
1673    test_impl! { vec_vmaxuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vmaxuh, vmaxuh] }
1674    test_impl! { vec_vmaxuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vmaxuw, vmaxuw] }
1675
1676    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1677    pub trait VectorMax<Other> {
1678        type Result;
1679        unsafe fn vec_max(self, b: Other) -> Self::Result;
1680    }
1681
1682    impl_vec_trait! { [VectorMax vec_max] ~(vmaxub, vmaxsb, vmaxuh, vmaxsh, vmaxuw, vmaxsw) }
1683
1684    #[inline]
1685    #[target_feature(enable = "altivec")]
1686    #[cfg_attr(test, assert_instr(vmuleub))]
1687    unsafe fn vec_vmuleub(
1688        a: vector_unsigned_char,
1689        b: vector_unsigned_char,
1690    ) -> vector_unsigned_short {
1691        vmuleub(a, b)
1692    }
1693    #[inline]
1694    #[target_feature(enable = "altivec")]
1695    #[cfg_attr(test, assert_instr(vmulesb))]
1696    unsafe fn vec_vmulesb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short {
1697        vmulesb(a, b)
1698    }
1699    #[inline]
1700    #[target_feature(enable = "altivec")]
1701    #[cfg_attr(test, assert_instr(vmuleuh))]
1702    unsafe fn vec_vmuleuh(
1703        a: vector_unsigned_short,
1704        b: vector_unsigned_short,
1705    ) -> vector_unsigned_int {
1706        vmuleuh(a, b)
1707    }
1708    #[inline]
1709    #[target_feature(enable = "altivec")]
1710    #[cfg_attr(test, assert_instr(vmulesh))]
1711    unsafe fn vec_vmulesh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int {
1712        vmulesh(a, b)
1713    }
1714
1715    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1716    pub trait VectorMul {
1717        unsafe fn vec_mul(self, b: Self) -> Self;
1718    }
1719
1720    #[inline]
1721    #[target_feature(enable = "altivec")]
1722    #[cfg_attr(test, assert_instr(vmuluwm))]
1723    unsafe fn vec_vmuluwm(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
1724        transmute(simd_mul::<i32x4>(transmute(a), transmute(b)))
1725    }
1726
1727    #[inline]
1728    #[target_feature(enable = "altivec")]
1729    #[cfg_attr(test, assert_instr(xvmulsp))]
1730    unsafe fn vec_xvmulsp(a: vector_float, b: vector_float) -> vector_float {
1731        transmute(simd_mul::<f32x4>(transmute(a), transmute(b)))
1732    }
1733
1734    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1735    impl VectorMul for vector_signed_int {
1736        #[inline]
1737        #[target_feature(enable = "altivec")]
1738        unsafe fn vec_mul(self, b: Self) -> Self {
1739            vec_vmuluwm(self, b)
1740        }
1741    }
1742
1743    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1744    impl VectorMul for vector_unsigned_int {
1745        #[inline]
1746        #[target_feature(enable = "altivec")]
1747        unsafe fn vec_mul(self, b: Self) -> Self {
1748            transmute(simd_mul::<u32x4>(transmute(self), transmute(b)))
1749        }
1750    }
1751
1752    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1753    impl VectorMul for vector_float {
1754        #[inline]
1755        #[target_feature(enable = "altivec")]
1756        unsafe fn vec_mul(self, b: Self) -> Self {
1757            vec_xvmulsp(self, b)
1758        }
1759    }
1760
1761    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1762    pub trait VectorMule<Result> {
1763        unsafe fn vec_mule(self, b: Self) -> Result;
1764    }
1765
1766    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1767    impl VectorMule<vector_unsigned_short> for vector_unsigned_char {
1768        #[inline]
1769        #[target_feature(enable = "altivec")]
1770        unsafe fn vec_mule(self, b: Self) -> vector_unsigned_short {
1771            vmuleub(self, b)
1772        }
1773    }
1774    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1775    impl VectorMule<vector_signed_short> for vector_signed_char {
1776        #[inline]
1777        #[target_feature(enable = "altivec")]
1778        unsafe fn vec_mule(self, b: Self) -> vector_signed_short {
1779            vmulesb(self, b)
1780        }
1781    }
1782    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1783    impl VectorMule<vector_unsigned_int> for vector_unsigned_short {
1784        #[inline]
1785        #[target_feature(enable = "altivec")]
1786        unsafe fn vec_mule(self, b: Self) -> vector_unsigned_int {
1787            vmuleuh(self, b)
1788        }
1789    }
1790    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1791    impl VectorMule<vector_signed_int> for vector_signed_short {
1792        #[inline]
1793        #[target_feature(enable = "altivec")]
1794        unsafe fn vec_mule(self, b: Self) -> vector_signed_int {
1795            vmulesh(self, b)
1796        }
1797    }
1798
1799    #[inline]
1800    #[target_feature(enable = "altivec")]
1801    #[cfg_attr(test, assert_instr(vmuloub))]
1802    unsafe fn vec_vmuloub(
1803        a: vector_unsigned_char,
1804        b: vector_unsigned_char,
1805    ) -> vector_unsigned_short {
1806        vmuloub(a, b)
1807    }
1808    #[inline]
1809    #[target_feature(enable = "altivec")]
1810    #[cfg_attr(test, assert_instr(vmulosb))]
1811    unsafe fn vec_vmulosb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_short {
1812        vmulosb(a, b)
1813    }
1814    #[inline]
1815    #[target_feature(enable = "altivec")]
1816    #[cfg_attr(test, assert_instr(vmulouh))]
1817    unsafe fn vec_vmulouh(
1818        a: vector_unsigned_short,
1819        b: vector_unsigned_short,
1820    ) -> vector_unsigned_int {
1821        vmulouh(a, b)
1822    }
1823    #[inline]
1824    #[target_feature(enable = "altivec")]
1825    #[cfg_attr(test, assert_instr(vmulosh))]
1826    unsafe fn vec_vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int {
1827        vmulosh(a, b)
1828    }
1829
1830    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1831    pub trait VectorMulo<Result> {
1832        unsafe fn vec_mulo(self, b: Self) -> Result;
1833    }
1834
1835    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1836    impl VectorMulo<vector_unsigned_short> for vector_unsigned_char {
1837        #[inline]
1838        #[target_feature(enable = "altivec")]
1839        unsafe fn vec_mulo(self, b: Self) -> vector_unsigned_short {
1840            vmuloub(self, b)
1841        }
1842    }
1843    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1844    impl VectorMulo<vector_signed_short> for vector_signed_char {
1845        #[inline]
1846        #[target_feature(enable = "altivec")]
1847        unsafe fn vec_mulo(self, b: Self) -> vector_signed_short {
1848            vmulosb(self, b)
1849        }
1850    }
1851    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1852    impl VectorMulo<vector_unsigned_int> for vector_unsigned_short {
1853        #[inline]
1854        #[target_feature(enable = "altivec")]
1855        unsafe fn vec_mulo(self, b: Self) -> vector_unsigned_int {
1856            vmulouh(self, b)
1857        }
1858    }
1859    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1860    impl VectorMulo<vector_signed_int> for vector_signed_short {
1861        #[inline]
1862        #[target_feature(enable = "altivec")]
1863        unsafe fn vec_mulo(self, b: Self) -> vector_signed_int {
1864            vmulosh(self, b)
1865        }
1866    }
1867
1868    #[inline]
1869    #[target_feature(enable = "altivec")]
1870    #[cfg_attr(test, assert_instr(vsum4ubs))]
1871    unsafe fn vec_vsum4ubs(a: vector_unsigned_char, b: vector_unsigned_int) -> vector_unsigned_int {
1872        vsum4ubs(a, b)
1873    }
1874
1875    #[inline]
1876    #[target_feature(enable = "altivec")]
1877    #[cfg_attr(test, assert_instr(vsum4sbs))]
1878    unsafe fn vec_vsum4sbs(a: vector_signed_char, b: vector_signed_int) -> vector_signed_int {
1879        vsum4sbs(a, b)
1880    }
1881
1882    #[inline]
1883    #[target_feature(enable = "altivec")]
1884    #[cfg_attr(test, assert_instr(vsum4shs))]
1885    unsafe fn vec_vsum4shs(a: vector_signed_short, b: vector_signed_int) -> vector_signed_int {
1886        vsum4shs(a, b)
1887    }
1888
1889    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1890    pub trait VectorSum4s<Other> {
1891        unsafe fn vec_sum4s(self, b: Other) -> Other;
1892    }
1893
1894    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1895    impl VectorSum4s<vector_unsigned_int> for vector_unsigned_char {
1896        #[inline]
1897        #[target_feature(enable = "altivec")]
1898        unsafe fn vec_sum4s(self, b: vector_unsigned_int) -> vector_unsigned_int {
1899            vsum4ubs(self, b)
1900        }
1901    }
1902
1903    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1904    impl VectorSum4s<vector_signed_int> for vector_signed_char {
1905        #[inline]
1906        #[target_feature(enable = "altivec")]
1907        unsafe fn vec_sum4s(self, b: vector_signed_int) -> vector_signed_int {
1908            vsum4sbs(self, b)
1909        }
1910    }
1911
1912    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1913    impl VectorSum4s<vector_signed_int> for vector_signed_short {
1914        #[inline]
1915        #[target_feature(enable = "altivec")]
1916        unsafe fn vec_sum4s(self, b: vector_signed_int) -> vector_signed_int {
1917            vsum4shs(self, b)
1918        }
1919    }
1920
1921    #[inline]
1922    #[target_feature(enable = "altivec")]
1923    #[cfg_attr(test, assert_instr(vsum2sws))]
1924    unsafe fn vec_vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
1925        vsum2sws(a, b)
1926    }
1927
1928    #[inline]
1929    #[target_feature(enable = "altivec")]
1930    #[cfg_attr(test, assert_instr(xvnmsubasp))]
1931    pub unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
1932        simd_neg(simd_fma(a, b, simd_neg(c)))
1933    }
1934
1935    #[inline]
1936    #[target_feature(enable = "altivec")]
1937    #[cfg_attr(test, assert_instr(xvmaddasp))]
1938    pub unsafe fn vec_vmaddfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
1939        simd_fma(a, b, c)
1940    }
1941
1942    #[inline]
1943    #[target_feature(enable = "altivec")]
1944    #[cfg_attr(test, assert_instr(vmsumubm))]
1945    unsafe fn vec_vmsumubm(
1946        a: vector_unsigned_char,
1947        b: vector_unsigned_char,
1948        c: vector_unsigned_int,
1949    ) -> vector_unsigned_int {
1950        vmsumubm(a, b, c)
1951    }
1952
1953    #[inline]
1954    #[target_feature(enable = "altivec")]
1955    #[cfg_attr(test, assert_instr(vmsummbm))]
1956    unsafe fn vec_vmsummbm(
1957        a: vector_signed_char,
1958        b: vector_unsigned_char,
1959        c: vector_signed_int,
1960    ) -> vector_signed_int {
1961        vmsummbm(a, b, c)
1962    }
1963
1964    #[inline]
1965    #[target_feature(enable = "altivec")]
1966    #[cfg_attr(test, assert_instr(vmsumuhm))]
1967    unsafe fn vec_vmsumuhm(
1968        a: vector_unsigned_short,
1969        b: vector_unsigned_short,
1970        c: vector_unsigned_int,
1971    ) -> vector_unsigned_int {
1972        vmsumuhm(a, b, c)
1973    }
1974
1975    #[inline]
1976    #[target_feature(enable = "altivec")]
1977    #[cfg_attr(test, assert_instr(vmsumshm))]
1978    unsafe fn vec_vmsumshm(
1979        a: vector_signed_short,
1980        b: vector_signed_short,
1981        c: vector_signed_int,
1982    ) -> vector_signed_int {
1983        vmsumshm(a, b, c)
1984    }
1985
1986    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1987    pub trait VectorMsum<B, Other> {
1988        unsafe fn vec_msum(self, b: B, c: Other) -> Other;
1989    }
1990
1991    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
1992    impl VectorMsum<vector_unsigned_char, vector_unsigned_int> for vector_unsigned_char {
1993        #[inline]
1994        #[target_feature(enable = "altivec")]
1995        unsafe fn vec_msum(
1996            self,
1997            b: vector_unsigned_char,
1998            c: vector_unsigned_int,
1999        ) -> vector_unsigned_int {
2000            vmsumubm(self, b, c)
2001        }
2002    }
2003
2004    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2005    impl VectorMsum<vector_unsigned_char, vector_signed_int> for vector_signed_char {
2006        #[inline]
2007        #[target_feature(enable = "altivec")]
2008        unsafe fn vec_msum(
2009            self,
2010            b: vector_unsigned_char,
2011            c: vector_signed_int,
2012        ) -> vector_signed_int {
2013            vmsummbm(self, b, c)
2014        }
2015    }
2016
2017    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2018    impl VectorMsum<vector_unsigned_short, vector_unsigned_int> for vector_unsigned_short {
2019        #[inline]
2020        #[target_feature(enable = "altivec")]
2021        unsafe fn vec_msum(
2022            self,
2023            b: vector_unsigned_short,
2024            c: vector_unsigned_int,
2025        ) -> vector_unsigned_int {
2026            vmsumuhm(self, b, c)
2027        }
2028    }
2029
2030    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2031    impl VectorMsum<vector_signed_short, vector_signed_int> for vector_signed_short {
2032        #[inline]
2033        #[target_feature(enable = "altivec")]
2034        unsafe fn vec_msum(
2035            self,
2036            b: vector_signed_short,
2037            c: vector_signed_int,
2038        ) -> vector_signed_int {
2039            vmsumshm(self, b, c)
2040        }
2041    }
2042
2043    #[inline]
2044    #[target_feature(enable = "altivec")]
2045    #[cfg_attr(test, assert_instr(vmsumuhs))]
2046    unsafe fn vec_vmsumuhs(
2047        a: vector_unsigned_short,
2048        b: vector_unsigned_short,
2049        c: vector_unsigned_int,
2050    ) -> vector_unsigned_int {
2051        vmsumuhs(a, b, c)
2052    }
2053
2054    #[inline]
2055    #[target_feature(enable = "altivec")]
2056    #[cfg_attr(test, assert_instr(vmsumshs))]
2057    unsafe fn vec_vmsumshs(
2058        a: vector_signed_short,
2059        b: vector_signed_short,
2060        c: vector_signed_int,
2061    ) -> vector_signed_int {
2062        vmsumshs(a, b, c)
2063    }
2064
2065    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2066    pub trait VectorMsums<Other> {
2067        unsafe fn vec_msums(self, b: Self, c: Other) -> Other;
2068    }
2069
2070    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2071    impl VectorMsums<vector_unsigned_int> for vector_unsigned_short {
2072        #[inline]
2073        #[target_feature(enable = "altivec")]
2074        unsafe fn vec_msums(self, b: Self, c: vector_unsigned_int) -> vector_unsigned_int {
2075            vmsumuhs(self, b, c)
2076        }
2077    }
2078
2079    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2080    impl VectorMsums<vector_signed_int> for vector_signed_short {
2081        #[inline]
2082        #[target_feature(enable = "altivec")]
2083        unsafe fn vec_msums(self, b: Self, c: vector_signed_int) -> vector_signed_int {
2084            vmsumshs(self, b, c)
2085        }
2086    }
2087
2088    #[inline]
2089    #[target_feature(enable = "altivec")]
2090    #[cfg_attr(test, assert_instr(vperm))]
2091    unsafe fn vec_vperm(
2092        a: vector_signed_int,
2093        b: vector_signed_int,
2094        c: vector_unsigned_char,
2095    ) -> vector_signed_int {
2096        vperm(a, b, c)
2097    }
2098
2099    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2100    pub trait VectorPerm {
2101        unsafe fn vec_vperm(self, b: Self, c: vector_unsigned_char) -> Self;
2102    }
2103
2104    macro_rules! vector_perm {
2105        {$impl: ident} => {
2106            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2107            impl VectorPerm for $impl {
2108            #[inline]
2109            #[target_feature(enable = "altivec")]
2110            unsafe fn vec_vperm(self, b: Self, c: vector_unsigned_char) -> Self {
2111                    transmute(vec_vperm(transmute(self), transmute(b), c))
2112                }
2113            }
2114        }
2115    }
2116
2117    vector_perm! { vector_signed_char }
2118    vector_perm! { vector_unsigned_char }
2119    vector_perm! { vector_bool_char }
2120
2121    vector_perm! { vector_signed_short }
2122    vector_perm! { vector_unsigned_short }
2123    vector_perm! { vector_bool_short }
2124
2125    vector_perm! { vector_signed_int }
2126    vector_perm! { vector_unsigned_int }
2127    vector_perm! { vector_bool_int }
2128
2129    vector_perm! { vector_float }
2130
2131    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2132    pub trait VectorAdd<Other> {
2133        type Result;
2134        unsafe fn vec_add(self, other: Other) -> Self::Result;
2135    }
2136
2137    #[inline]
2138    #[target_feature(enable = "altivec")]
2139    #[cfg_attr(test, assert_instr(vaddubm))]
2140    pub unsafe fn vec_add_bc_sc(a: vector_bool_char, b: vector_signed_char) -> vector_signed_char {
2141        simd_add(transmute(a), b)
2142    }
2143    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2144    impl VectorAdd<vector_signed_char> for vector_bool_char {
2145        type Result = vector_signed_char;
2146        #[inline]
2147        #[target_feature(enable = "altivec")]
2148        unsafe fn vec_add(self, other: vector_signed_char) -> Self::Result {
2149            vec_add_bc_sc(self, other)
2150        }
2151    }
2152    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2153    impl VectorAdd<vector_bool_char> for vector_signed_char {
2154        type Result = vector_signed_char;
2155        #[inline]
2156        #[target_feature(enable = "altivec")]
2157        unsafe fn vec_add(self, other: vector_bool_char) -> Self::Result {
2158            other.vec_add(self)
2159        }
2160    }
2161
2162    #[inline]
2163    #[target_feature(enable = "altivec")]
2164    #[cfg_attr(test, assert_instr(vaddubm))]
2165    pub unsafe fn vec_add_sc_sc(
2166        a: vector_signed_char,
2167        b: vector_signed_char,
2168    ) -> vector_signed_char {
2169        simd_add(a, b)
2170    }
2171    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2172    impl VectorAdd<vector_signed_char> for vector_signed_char {
2173        type Result = vector_signed_char;
2174        #[inline]
2175        #[target_feature(enable = "altivec")]
2176        unsafe fn vec_add(self, other: vector_signed_char) -> Self::Result {
2177            vec_add_sc_sc(self, other)
2178        }
2179    }
2180
2181    #[inline]
2182    #[target_feature(enable = "altivec")]
2183    #[cfg_attr(test, assert_instr(vaddubm))]
2184    pub unsafe fn vec_add_bc_uc(
2185        a: vector_bool_char,
2186        b: vector_unsigned_char,
2187    ) -> vector_unsigned_char {
2188        simd_add(transmute(a), b)
2189    }
2190    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2191    impl VectorAdd<vector_unsigned_char> for vector_bool_char {
2192        type Result = vector_unsigned_char;
2193        #[inline]
2194        #[target_feature(enable = "altivec")]
2195        unsafe fn vec_add(self, other: vector_unsigned_char) -> Self::Result {
2196            vec_add_bc_uc(self, other)
2197        }
2198    }
2199    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2200    impl VectorAdd<vector_bool_char> for vector_unsigned_char {
2201        type Result = vector_unsigned_char;
2202        #[inline]
2203        #[target_feature(enable = "altivec")]
2204        unsafe fn vec_add(self, other: vector_bool_char) -> Self::Result {
2205            other.vec_add(self)
2206        }
2207    }
2208
2209    #[inline]
2210    #[target_feature(enable = "altivec")]
2211    #[cfg_attr(test, assert_instr(vaddubm))]
2212    pub unsafe fn vec_add_uc_uc(
2213        a: vector_unsigned_char,
2214        b: vector_unsigned_char,
2215    ) -> vector_unsigned_char {
2216        simd_add(a, b)
2217    }
2218    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2219    impl VectorAdd<vector_unsigned_char> for vector_unsigned_char {
2220        type Result = vector_unsigned_char;
2221        #[inline]
2222        #[target_feature(enable = "altivec")]
2223        unsafe fn vec_add(self, other: vector_unsigned_char) -> Self::Result {
2224            vec_add_uc_uc(self, other)
2225        }
2226    }
2227
2228    #[inline]
2229    #[target_feature(enable = "altivec")]
2230    #[cfg_attr(test, assert_instr(vadduhm))]
2231    pub unsafe fn vec_add_bs_ss(
2232        a: vector_bool_short,
2233        b: vector_signed_short,
2234    ) -> vector_signed_short {
2235        let a: i16x8 = transmute(a);
2236        let a: vector_signed_short = simd_cast(a);
2237        simd_add(a, b)
2238    }
2239
2240    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2241    impl VectorAdd<vector_signed_short> for vector_bool_short {
2242        type Result = vector_signed_short;
2243        #[inline]
2244        #[target_feature(enable = "altivec")]
2245        unsafe fn vec_add(self, other: vector_signed_short) -> Self::Result {
2246            vec_add_bs_ss(self, other)
2247        }
2248    }
2249    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2250    impl VectorAdd<vector_bool_short> for vector_signed_short {
2251        type Result = vector_signed_short;
2252        #[inline]
2253        #[target_feature(enable = "altivec")]
2254        unsafe fn vec_add(self, other: vector_bool_short) -> Self::Result {
2255            other.vec_add(self)
2256        }
2257    }
2258
2259    #[inline]
2260    #[target_feature(enable = "altivec")]
2261    #[cfg_attr(test, assert_instr(vadduhm))]
2262    pub unsafe fn vec_add_ss_ss(
2263        a: vector_signed_short,
2264        b: vector_signed_short,
2265    ) -> vector_signed_short {
2266        simd_add(a, b)
2267    }
2268    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2269    impl VectorAdd<vector_signed_short> for vector_signed_short {
2270        type Result = vector_signed_short;
2271        #[inline]
2272        #[target_feature(enable = "altivec")]
2273        unsafe fn vec_add(self, other: vector_signed_short) -> Self::Result {
2274            vec_add_ss_ss(self, other)
2275        }
2276    }
2277
2278    #[inline]
2279    #[target_feature(enable = "altivec")]
2280    #[cfg_attr(test, assert_instr(vadduhm))]
2281    pub unsafe fn vec_add_bs_us(
2282        a: vector_bool_short,
2283        b: vector_unsigned_short,
2284    ) -> vector_unsigned_short {
2285        let a: i16x8 = transmute(a);
2286        let a: vector_unsigned_short = simd_cast(a);
2287        simd_add(a, b)
2288    }
2289    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2290    impl VectorAdd<vector_unsigned_short> for vector_bool_short {
2291        type Result = vector_unsigned_short;
2292        #[inline]
2293        #[target_feature(enable = "altivec")]
2294        unsafe fn vec_add(self, other: vector_unsigned_short) -> Self::Result {
2295            vec_add_bs_us(self, other)
2296        }
2297    }
2298    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2299    impl VectorAdd<vector_bool_short> for vector_unsigned_short {
2300        type Result = vector_unsigned_short;
2301        #[inline]
2302        #[target_feature(enable = "altivec")]
2303        unsafe fn vec_add(self, other: vector_bool_short) -> Self::Result {
2304            other.vec_add(self)
2305        }
2306    }
2307
2308    #[inline]
2309    #[target_feature(enable = "altivec")]
2310    #[cfg_attr(test, assert_instr(vadduhm))]
2311    pub unsafe fn vec_add_us_us(
2312        a: vector_unsigned_short,
2313        b: vector_unsigned_short,
2314    ) -> vector_unsigned_short {
2315        simd_add(a, b)
2316    }
2317
2318    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2319    impl VectorAdd<vector_unsigned_short> for vector_unsigned_short {
2320        type Result = vector_unsigned_short;
2321        #[inline]
2322        #[target_feature(enable = "altivec")]
2323        unsafe fn vec_add(self, other: vector_unsigned_short) -> Self::Result {
2324            vec_add_us_us(self, other)
2325        }
2326    }
2327
2328    #[inline]
2329    #[target_feature(enable = "altivec")]
2330    #[cfg_attr(test, assert_instr(vadduwm))]
2331    pub unsafe fn vec_add_bi_si(a: vector_bool_int, b: vector_signed_int) -> vector_signed_int {
2332        let a: i32x4 = transmute(a);
2333        let a: vector_signed_int = simd_cast(a);
2334        simd_add(a, b)
2335    }
2336    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2337    impl VectorAdd<vector_signed_int> for vector_bool_int {
2338        type Result = vector_signed_int;
2339        #[inline]
2340        #[target_feature(enable = "altivec")]
2341        unsafe fn vec_add(self, other: vector_signed_int) -> Self::Result {
2342            vec_add_bi_si(self, other)
2343        }
2344    }
2345    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2346    impl VectorAdd<vector_bool_int> for vector_signed_int {
2347        type Result = vector_signed_int;
2348        #[inline]
2349        #[target_feature(enable = "altivec")]
2350        unsafe fn vec_add(self, other: vector_bool_int) -> Self::Result {
2351            other.vec_add(self)
2352        }
2353    }
2354
2355    #[inline]
2356    #[target_feature(enable = "altivec")]
2357    #[cfg_attr(test, assert_instr(vadduwm))]
2358    pub unsafe fn vec_add_si_si(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
2359        simd_add(a, b)
2360    }
2361    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2362    impl VectorAdd<vector_signed_int> for vector_signed_int {
2363        type Result = vector_signed_int;
2364        #[inline]
2365        #[target_feature(enable = "altivec")]
2366        unsafe fn vec_add(self, other: vector_signed_int) -> Self::Result {
2367            vec_add_si_si(self, other)
2368        }
2369    }
2370
2371    #[inline]
2372    #[target_feature(enable = "altivec")]
2373    #[cfg_attr(test, assert_instr(vadduwm))]
2374    pub unsafe fn vec_add_bi_ui(a: vector_bool_int, b: vector_unsigned_int) -> vector_unsigned_int {
2375        let a: i32x4 = transmute(a);
2376        let a: vector_unsigned_int = simd_cast(a);
2377        simd_add(a, b)
2378    }
2379    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2380    impl VectorAdd<vector_unsigned_int> for vector_bool_int {
2381        type Result = vector_unsigned_int;
2382        #[inline]
2383        #[target_feature(enable = "altivec")]
2384        unsafe fn vec_add(self, other: vector_unsigned_int) -> Self::Result {
2385            vec_add_bi_ui(self, other)
2386        }
2387    }
2388    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2389    impl VectorAdd<vector_bool_int> for vector_unsigned_int {
2390        type Result = vector_unsigned_int;
2391        #[inline]
2392        #[target_feature(enable = "altivec")]
2393        unsafe fn vec_add(self, other: vector_bool_int) -> Self::Result {
2394            other.vec_add(self)
2395        }
2396    }
2397
2398    #[inline]
2399    #[target_feature(enable = "altivec")]
2400    #[cfg_attr(test, assert_instr(vadduwm))]
2401    pub unsafe fn vec_add_ui_ui(
2402        a: vector_unsigned_int,
2403        b: vector_unsigned_int,
2404    ) -> vector_unsigned_int {
2405        simd_add(a, b)
2406    }
2407    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2408    impl VectorAdd<vector_unsigned_int> for vector_unsigned_int {
2409        type Result = vector_unsigned_int;
2410        #[inline]
2411        #[target_feature(enable = "altivec")]
2412        unsafe fn vec_add(self, other: vector_unsigned_int) -> Self::Result {
2413            vec_add_ui_ui(self, other)
2414        }
2415    }
2416
2417    #[inline]
2418    #[target_feature(enable = "altivec")]
2419    #[cfg_attr(test, assert_instr(xvaddsp))]
2420    pub unsafe fn vec_add_float_float(a: vector_float, b: vector_float) -> vector_float {
2421        simd_add(a, b)
2422    }
2423
2424    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2425    impl VectorAdd<vector_float> for vector_float {
2426        type Result = vector_float;
2427        #[inline]
2428        #[target_feature(enable = "altivec")]
2429        unsafe fn vec_add(self, other: vector_float) -> Self::Result {
2430            vec_add_float_float(self, other)
2431        }
2432    }
2433
2434    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2435    pub trait VectorAdde {
2436        unsafe fn vec_adde(self, b: Self, c: Self) -> Self;
2437    }
2438
2439    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2440    impl VectorAdde for vector_unsigned_int {
2441        #[inline]
2442        #[target_feature(enable = "altivec")]
2443        unsafe fn vec_adde(self, b: Self, c: Self) -> Self {
2444            let mask: vector_unsigned_int = transmute(u32x4::new(1, 1, 1, 1));
2445            let carry = vec_and(c, mask);
2446            vec_add(vec_add(self, b), carry)
2447        }
2448    }
2449
2450    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2451    impl VectorAdde for vector_signed_int {
2452        #[inline]
2453        #[target_feature(enable = "altivec")]
2454        unsafe fn vec_adde(self, b: Self, c: Self) -> Self {
2455            let mask: vector_signed_int = transmute(i32x4::new(1, 1, 1, 1));
2456            let carry = vec_and(c, mask);
2457            vec_add(vec_add(self, b), carry)
2458        }
2459    }
2460
2461    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2462    pub trait VectorMladd<Other> {
2463        type Result;
2464        unsafe fn vec_mladd(self, b: Other, c: Other) -> Self::Result;
2465    }
2466
2467    #[inline]
2468    #[target_feature(enable = "altivec")]
2469    #[cfg_attr(test, assert_instr(vmladduhm))]
2470    unsafe fn mladd(
2471        a: vector_signed_short,
2472        b: vector_signed_short,
2473        c: vector_signed_short,
2474    ) -> vector_signed_short {
2475        let a: i16x8 = transmute(a);
2476        let b: i16x8 = transmute(b);
2477        let c: i16x8 = transmute(c);
2478        transmute(simd_add(simd_mul(a, b), c))
2479    }
2480
2481    macro_rules! vector_mladd {
2482        ($a: ident, $bc: ident, $d: ident) => {
2483            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2484            impl VectorMladd<$bc> for $a {
2485                type Result = $d;
2486                #[inline]
2487                #[target_feature(enable = "altivec")]
2488                unsafe fn vec_mladd(self, b: $bc, c: $bc) -> Self::Result {
2489                    let a = transmute(self);
2490                    let b = transmute(b);
2491                    let c = transmute(c);
2492
2493                    transmute(mladd(a, b, c))
2494                }
2495            }
2496        };
2497    }
2498
2499    vector_mladd! { vector_unsigned_short, vector_unsigned_short, vector_unsigned_short }
2500    vector_mladd! { vector_unsigned_short, vector_signed_short, vector_signed_short }
2501    vector_mladd! { vector_signed_short, vector_unsigned_short, vector_signed_short }
2502    vector_mladd! { vector_signed_short, vector_signed_short, vector_signed_short }
2503
2504    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2505    pub trait VectorOr<Other> {
2506        type Result;
2507        unsafe fn vec_or(self, b: Other) -> Self::Result;
2508    }
2509
2510    impl_vec_trait! { [VectorOr vec_or] ~(simd_or) }
2511
2512    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2513    pub trait VectorXor<Other> {
2514        type Result;
2515        unsafe fn vec_xor(self, b: Other) -> Self::Result;
2516    }
2517
2518    impl_vec_trait! { [VectorXor vec_xor] ~(simd_xor) }
2519
2520    macro_rules! vector_vnor {
2521        ($fun:ident $ty:ident) => {
2522            #[inline]
2523            #[target_feature(enable = "altivec")]
2524            #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vnor))]
2525            #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlnor))]
2526            pub unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
2527                let o = vec_splats(!0 as $ty);
2528                vec_xor(vec_or(a, b), o)
2529            }
2530        };
2531    }
2532
2533    vector_vnor! { vec_vnorsb i8 }
2534    vector_vnor! { vec_vnorsh i16 }
2535    vector_vnor! { vec_vnorsw i32 }
2536
2537    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2538    pub trait VectorNor<Other> {
2539        type Result;
2540        unsafe fn vec_nor(self, b: Other) -> Self::Result;
2541    }
2542
2543    impl_vec_trait! { [VectorNor vec_nor]+ 2b (vec_vnorsb, vec_vnorsh, vec_vnorsw) }
2544
2545    macro_rules! vector_vnand {
2546        ($fun:ident $ty:ident) => {
2547            #[inline]
2548            #[target_feature(enable = "altivec")]
2549            #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vnand))]
2550            #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlnand))]
2551            pub unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
2552                let o = vec_splats(!0 as $ty);
2553                vec_xor(vec_and(a, b), o)
2554            }
2555        };
2556    }
2557
2558    vector_vnand! { vec_vnandsb i8 }
2559    vector_vnand! { vec_vnandsh i16 }
2560    vector_vnand! { vec_vnandsw i32 }
2561
2562    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2563    pub trait VectorNand<Other> {
2564        type Result;
2565        unsafe fn vec_nand(self, b: Other) -> Self::Result;
2566    }
2567
2568    impl_vec_trait! { [VectorNand vec_nand]+ 2b (vec_vnandsb, vec_vnandsh, vec_vnandsw) }
2569
2570    #[inline]
2571    #[target_feature(enable = "altivec")]
2572    #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vsel))]
2573    #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxsel))]
2574    pub unsafe fn vec_vsel(
2575        a: vector_signed_char,
2576        b: vector_signed_char,
2577        c: vector_signed_char,
2578    ) -> vector_signed_char {
2579        let a: i8x16 = transmute(a);
2580        let b: i8x16 = transmute(b);
2581        let c: i8x16 = transmute(c);
2582        let not_c = simd_xor(c, i8x16::splat(!0));
2583
2584        transmute(simd_or(simd_and(a, not_c), simd_and(b, c)))
2585    }
2586
2587    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2588    pub trait VectorSel<Mask> {
2589        unsafe fn vec_sel(self, b: Self, c: Mask) -> Self;
2590    }
2591
2592    macro_rules! vector_sel {
2593        ($ty: ty, $m: ty) => {
2594            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2595            impl VectorSel<$m> for $ty {
2596                #[inline]
2597                #[target_feature(enable = "altivec")]
2598                unsafe fn vec_sel(self, b: Self, c: $m) -> Self {
2599                    let a = transmute(self);
2600                    let b = transmute(b);
2601                    let c = transmute(c);
2602
2603                    transmute(vec_vsel(a, b, c))
2604                }
2605            }
2606        };
2607        ($ty: ident) => {
2608            vector_sel! { $ty, t_b!{ $ty } }
2609            vector_sel! { $ty, t_u!{ $ty } }
2610            vector_sel! { t_u!{ $ty }, t_b!{ $ty } }
2611            vector_sel! { t_u!{ $ty }, t_u!{ $ty } }
2612            vector_sel! { t_b!{ $ty }, t_b!{ $ty } }
2613            vector_sel! { t_b!{ $ty }, t_u!{ $ty } }
2614        };
2615        (- $ty: ident) => {
2616            vector_sel! { $ty, t_b!{ $ty } }
2617            vector_sel! { $ty, t_u!{ $ty } }
2618        };
2619    }
2620
2621    vector_sel! { vector_signed_char }
2622    vector_sel! { vector_signed_short }
2623    vector_sel! { vector_signed_int }
2624    vector_sel! {- vector_float }
2625
2626    #[inline]
2627    #[target_feature(enable = "altivec")]
2628    #[cfg_attr(test, assert_instr(vcfsx, IMM5 = 1))]
2629    unsafe fn vec_ctf_i32<const IMM5: i32>(a: vector_signed_int) -> vector_float {
2630        static_assert_uimm_bits!(IMM5, 5);
2631        vcfsx(a, IMM5)
2632    }
2633
2634    #[inline]
2635    #[target_feature(enable = "altivec")]
2636    #[cfg_attr(test, assert_instr(vcfux, IMM5 = 1))]
2637    unsafe fn vec_ctf_u32<const IMM5: i32>(a: vector_unsigned_int) -> vector_float {
2638        static_assert_uimm_bits!(IMM5, 5);
2639        vcfux(a, IMM5)
2640    }
2641
2642    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2643    pub trait VectorCtf {
2644        unsafe fn vec_ctf<const IMM5: i32>(self) -> vector_float;
2645    }
2646
2647    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2648    impl VectorCtf for vector_signed_int {
2649        unsafe fn vec_ctf<const IMM5: i32>(self) -> vector_float {
2650            vec_ctf_i32::<IMM5>(self)
2651        }
2652    }
2653
2654    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2655    impl VectorCtf for vector_unsigned_int {
2656        unsafe fn vec_ctf<const IMM5: i32>(self) -> vector_float {
2657            vec_ctf_u32::<IMM5>(self)
2658        }
2659    }
2660
2661    #[inline]
2662    #[target_feature(enable = "altivec")]
2663    #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrghb))]
2664    #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrglb))]
2665    unsafe fn vec_vmrglb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
2666        let mergel_perm = transmute(u8x16::new(
2667            0x08, 0x18, 0x09, 0x19, 0x0A, 0x1A, 0x0B, 0x1B, 0x0C, 0x1C, 0x0D, 0x1D, 0x0E, 0x1E,
2668            0x0F, 0x1F,
2669        ));
2670        vec_perm(a, b, mergel_perm)
2671    }
2672
2673    #[inline]
2674    #[target_feature(enable = "altivec")]
2675    #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrghh))]
2676    #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrglh))]
2677    unsafe fn vec_vmrglh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short {
2678        let mergel_perm = transmute(u8x16::new(
2679            0x08, 0x09, 0x18, 0x19, 0x0A, 0x0B, 0x1A, 0x1B, 0x0C, 0x0D, 0x1C, 0x1D, 0x0E, 0x0F,
2680            0x1E, 0x1F,
2681        ));
2682        vec_perm(a, b, mergel_perm)
2683    }
2684
2685    #[inline]
2686    #[target_feature(enable = "altivec")]
2687    #[cfg_attr(
2688        all(test, target_endian = "little", not(target_feature = "vsx")),
2689        assert_instr(vmrghw)
2690    )]
2691    #[cfg_attr(
2692        all(test, target_endian = "little", target_feature = "vsx"),
2693        assert_instr(xxmrghw)
2694    )]
2695    #[cfg_attr(
2696        all(test, target_endian = "big", not(target_feature = "vsx")),
2697        assert_instr(vmrglw)
2698    )]
2699    #[cfg_attr(
2700        all(test, target_endian = "big", target_feature = "vsx"),
2701        assert_instr(xxmrglw)
2702    )]
2703    unsafe fn vec_vmrglw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
2704        let mergel_perm = transmute(u8x16::new(
2705            0x08, 0x09, 0x0A, 0x0B, 0x18, 0x19, 0x1A, 0x1B, 0x0C, 0x0D, 0x0E, 0x0F, 0x1C, 0x1D,
2706            0x1E, 0x1F,
2707        ));
2708        vec_perm(a, b, mergel_perm)
2709    }
2710
2711    #[inline]
2712    #[target_feature(enable = "altivec")]
2713    #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrglb))]
2714    #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrghb))]
2715    unsafe fn vec_vmrghb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char {
2716        let mergel_perm = transmute(u8x16::new(
2717            0x00, 0x10, 0x01, 0x11, 0x02, 0x12, 0x03, 0x13, 0x04, 0x14, 0x05, 0x15, 0x06, 0x16,
2718            0x07, 0x17,
2719        ));
2720        vec_perm(a, b, mergel_perm)
2721    }
2722
2723    #[inline]
2724    #[target_feature(enable = "altivec")]
2725    #[cfg_attr(all(test, target_endian = "little"), assert_instr(vmrglh))]
2726    #[cfg_attr(all(test, target_endian = "big"), assert_instr(vmrghh))]
2727    unsafe fn vec_vmrghh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short {
2728        let mergel_perm = transmute(u8x16::new(
2729            0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13, 0x04, 0x05, 0x14, 0x15, 0x06, 0x07,
2730            0x16, 0x17,
2731        ));
2732        vec_perm(a, b, mergel_perm)
2733    }
2734
2735    #[inline]
2736    #[target_feature(enable = "altivec")]
2737    #[cfg_attr(
2738        all(test, target_endian = "little", not(target_feature = "vsx")),
2739        assert_instr(vmrglw)
2740    )]
2741    #[cfg_attr(
2742        all(test, target_endian = "little", target_feature = "vsx"),
2743        assert_instr(xxmrglw)
2744    )]
2745    #[cfg_attr(
2746        all(test, target_endian = "big", not(target_feature = "vsx")),
2747        assert_instr(vmrghw)
2748    )]
2749    #[cfg_attr(
2750        all(test, target_endian = "big", target_feature = "vsx"),
2751        assert_instr(xxmrghw)
2752    )]
2753    unsafe fn vec_vmrghw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
2754        let mergel_perm = transmute(u8x16::new(
2755            0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13, 0x04, 0x05, 0x06, 0x07, 0x14, 0x15,
2756            0x16, 0x17,
2757        ));
2758        vec_perm(a, b, mergel_perm)
2759    }
2760
2761    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2762    pub trait VectorMergeh<Other> {
2763        type Result;
2764        unsafe fn vec_mergeh(self, b: Other) -> Self::Result;
2765    }
2766
2767    impl_vec_trait! { [VectorMergeh vec_mergeh]+ 2b (vec_vmrghb, vec_vmrghh, vec_vmrghw) }
2768    impl_vec_trait! { [VectorMergeh vec_mergeh]+ vec_vmrghw (vector_float, vector_float) -> vector_float }
2769
2770    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2771    pub trait VectorMergel<Other> {
2772        type Result;
2773        unsafe fn vec_mergel(self, b: Other) -> Self::Result;
2774    }
2775
2776    impl_vec_trait! { [VectorMergel vec_mergel]+ 2b (vec_vmrglb, vec_vmrglh, vec_vmrglw) }
2777    impl_vec_trait! { [VectorMergel vec_mergel]+ vec_vmrglw (vector_float, vector_float) -> vector_float }
2778
2779    #[inline]
2780    #[target_feature(enable = "altivec")]
2781    #[cfg_attr(test, assert_instr(vpkuhum))]
2782    unsafe fn vec_vpkuhum(a: vector_signed_short, b: vector_signed_short) -> vector_signed_char {
2783        let pack_perm = if cfg!(target_endian = "little") {
2784            transmute(u8x16::new(
2785                0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A,
2786                0x1C, 0x1E,
2787            ))
2788        } else {
2789            transmute(u8x16::new(
2790                0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1B,
2791                0x1D, 0x1F,
2792            ))
2793        };
2794
2795        transmute(vec_perm(a, b, pack_perm))
2796    }
2797
2798    #[inline]
2799    #[target_feature(enable = "altivec")]
2800    #[cfg_attr(test, assert_instr(vpkuwum))]
2801    unsafe fn vec_vpkuwum(a: vector_signed_int, b: vector_signed_int) -> vector_signed_short {
2802        let pack_perm = if cfg!(target_endian = "little") {
2803            transmute(u8x16::new(
2804                0x00, 0x01, 0x04, 0x05, 0x08, 0x09, 0x0C, 0x0D, 0x10, 0x11, 0x14, 0x15, 0x18, 0x19,
2805                0x1C, 0x1D,
2806            ))
2807        } else {
2808            transmute(u8x16::new(
2809                0x02, 0x03, 0x06, 0x07, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17, 0x1A, 0x1B,
2810                0x1E, 0x1F,
2811            ))
2812        };
2813
2814        transmute(vec_perm(a, b, pack_perm))
2815    }
2816
2817    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2818    pub trait VectorPack<Other> {
2819        type Result;
2820        unsafe fn vec_pack(self, b: Other) -> Self::Result;
2821    }
2822
2823    impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuhum (vector_signed_short, vector_signed_short) -> vector_signed_char }
2824    impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuhum (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_char }
2825    impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuhum (vector_bool_short, vector_bool_short) -> vector_bool_char }
2826    impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuwum (vector_signed_int, vector_signed_int) -> vector_signed_short }
2827    impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuwum (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
2828    impl_vec_trait! { [VectorPack vec_pack]+ vec_vpkuwum (vector_bool_int, vector_bool_int) -> vector_bool_short }
2829
2830    #[inline]
2831    #[target_feature(enable = "altivec")]
2832    #[cfg_attr(test, assert_instr(vpkshss))]
2833    unsafe fn vec_vpkshss(a: vector_signed_short, b: vector_signed_short) -> vector_signed_char {
2834        if cfg!(target_endian = "little") {
2835            vpkshss(b, a)
2836        } else {
2837            vpkshss(a, b)
2838        }
2839    }
2840
2841    #[inline]
2842    #[target_feature(enable = "altivec")]
2843    #[cfg_attr(test, assert_instr(vpkshus))]
2844    unsafe fn vec_vpkshus(a: vector_signed_short, b: vector_signed_short) -> vector_unsigned_char {
2845        if cfg!(target_endian = "little") {
2846            vpkshus(b, a)
2847        } else {
2848            vpkshus(a, b)
2849        }
2850    }
2851
2852    #[inline]
2853    #[target_feature(enable = "altivec")]
2854    #[cfg_attr(test, assert_instr(vpkuhus))]
2855    unsafe fn vec_vpkuhus(
2856        a: vector_unsigned_short,
2857        b: vector_unsigned_short,
2858    ) -> vector_unsigned_char {
2859        if cfg!(target_endian = "little") {
2860            vpkuhus(b, a)
2861        } else {
2862            vpkuhus(a, b)
2863        }
2864    }
2865
2866    #[inline]
2867    #[target_feature(enable = "altivec")]
2868    #[cfg_attr(test, assert_instr(vpkswss))]
2869    unsafe fn vec_vpkswss(a: vector_signed_int, b: vector_signed_int) -> vector_signed_short {
2870        if cfg!(target_endian = "little") {
2871            vpkswss(b, a)
2872        } else {
2873            vpkswss(a, b)
2874        }
2875    }
2876
2877    #[inline]
2878    #[target_feature(enable = "altivec")]
2879    #[cfg_attr(test, assert_instr(vpkswus))]
2880    unsafe fn vec_vpkswus(a: vector_signed_int, b: vector_signed_int) -> vector_unsigned_short {
2881        if cfg!(target_endian = "little") {
2882            vpkswus(b, a)
2883        } else {
2884            vpkswus(a, b)
2885        }
2886    }
2887
2888    #[inline]
2889    #[target_feature(enable = "altivec")]
2890    #[cfg_attr(test, assert_instr(vpkuwus))]
2891    unsafe fn vec_vpkuwus(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_short {
2892        if cfg!(target_endian = "little") {
2893            vpkuwus(b, a)
2894        } else {
2895            vpkuwus(a, b)
2896        }
2897    }
2898
2899    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2900    pub trait VectorPacks<Other> {
2901        type Result;
2902        unsafe fn vec_packs(self, b: Other) -> Self::Result;
2903    }
2904
2905    impl_vec_trait! { [VectorPacks vec_packs] vec_vpkshss (vector_signed_short, vector_signed_short) -> vector_signed_char }
2906    impl_vec_trait! { [VectorPacks vec_packs] vec_vpkuhus (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_char }
2907    impl_vec_trait! { [VectorPacks vec_packs] vec_vpkswss (vector_signed_int, vector_signed_int) -> vector_signed_short }
2908    impl_vec_trait! { [VectorPacks vec_packs] vec_vpkuwus (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
2909
2910    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2911    pub trait VectorPacksu<Other> {
2912        type Result;
2913        unsafe fn vec_packsu(self, b: Other) -> Self::Result;
2914    }
2915
2916    impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkshus (vector_signed_short, vector_signed_short) -> vector_unsigned_char }
2917    impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkuhus (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_char }
2918    impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkswus (vector_signed_int, vector_signed_int) -> vector_unsigned_short }
2919    impl_vec_trait! { [VectorPacksu vec_packsu] vec_vpkuwus (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
2920
2921    macro_rules! impl_vec_unpack {
2922        ($fun:ident ($a:ident) -> $r:ident [$little:ident, $big:ident]) => {
2923            #[inline]
2924            #[target_feature(enable = "altivec")]
2925            #[cfg_attr(all(test, target_endian = "little"), assert_instr($little))]
2926            #[cfg_attr(all(test, target_endian = "big"), assert_instr($big))]
2927            unsafe fn $fun(a: $a) -> $r {
2928                if cfg!(target_endian = "little") {
2929                    $little(a)
2930                } else {
2931                    $big(a)
2932                }
2933            }
2934        };
2935    }
2936
2937    impl_vec_unpack! { vec_vupkhsb (vector_signed_char) -> vector_signed_short [vupklsb, vupkhsb] }
2938    impl_vec_unpack! { vec_vupklsb (vector_signed_char) -> vector_signed_short [vupkhsb, vupklsb] }
2939    impl_vec_unpack! { vec_vupkhsh (vector_signed_short) -> vector_signed_int [vupklsh, vupkhsh] }
2940    impl_vec_unpack! { vec_vupklsh (vector_signed_short) -> vector_signed_int [vupkhsh, vupklsh] }
2941
2942    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2943    pub trait VectorUnpackh {
2944        type Result;
2945        unsafe fn vec_unpackh(self) -> Self::Result;
2946    }
2947
2948    impl_vec_trait! { [VectorUnpackh vec_unpackh] vec_vupkhsb (vector_signed_char) -> vector_signed_short }
2949    impl_vec_trait! { [VectorUnpackh vec_unpackh]+ vec_vupkhsb (vector_bool_char) -> vector_bool_short }
2950    impl_vec_trait! { [VectorUnpackh vec_unpackh] vec_vupkhsh (vector_signed_short) -> vector_signed_int }
2951    impl_vec_trait! { [VectorUnpackh vec_unpackh]+ vec_vupkhsh (vector_bool_short) -> vector_bool_int }
2952
2953    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2954    pub trait VectorUnpackl {
2955        type Result;
2956        unsafe fn vec_unpackl(self) -> Self::Result;
2957    }
2958
2959    impl_vec_trait! { [VectorUnpackl vec_unpackl] vec_vupklsb (vector_signed_char) -> vector_signed_short }
2960    impl_vec_trait! { [VectorUnpackl vec_unpackl]+ vec_vupklsb (vector_bool_char) -> vector_bool_short }
2961    impl_vec_trait! { [VectorUnpackl vec_unpackl] vec_vupklsh (vector_signed_short) -> vector_signed_int }
2962    impl_vec_trait! { [VectorUnpackl vec_unpackl]+ vec_vupklsh (vector_bool_short) -> vector_bool_int }
2963
2964    macro_rules! impl_vec_shift {
2965        ([$Trait:ident $m:ident] ($b:ident, $h:ident, $w:ident)) => {
2966            impl_vec_trait!{ [$Trait $m]+ $b (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
2967            impl_vec_trait!{ [$Trait $m]+ $b (vector_signed_char, vector_unsigned_char) -> vector_signed_char }
2968            impl_vec_trait!{ [$Trait $m]+ $h (vector_unsigned_short, vector_unsigned_short) -> vector_unsigned_short }
2969            impl_vec_trait!{ [$Trait $m]+ $h (vector_signed_short, vector_unsigned_short) -> vector_signed_short }
2970            impl_vec_trait!{ [$Trait $m]+ $w (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_int }
2971            impl_vec_trait!{ [$Trait $m]+ $w (vector_signed_int, vector_unsigned_int) -> vector_signed_int }
2972        };
2973    }
2974
2975    macro_rules! impl_shift {
2976        ($fun:ident $intr:ident $ty:ident) => {
2977            #[inline]
2978            #[target_feature(enable = "altivec")]
2979            #[cfg_attr(test, assert_instr($fun))]
2980            unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
2981                let a = transmute(a);
2982                let b = simd_rem(
2983                    transmute(b),
2984                    <t_t_s!($ty)>::splat(mem::size_of::<$ty>() as $ty * $ty::BITS as $ty),
2985                );
2986
2987                transmute($intr(a, b))
2988            }
2989        };
2990    }
2991
2992    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
2993    pub trait VectorSl<Other> {
2994        type Result;
2995        unsafe fn vec_sl(self, b: Other) -> Self::Result;
2996    }
2997
2998    impl_shift! { vslb simd_shl u8 }
2999    impl_shift! { vslh simd_shl u16 }
3000    impl_shift! { vslw simd_shl u32 }
3001
3002    impl_vec_shift! { [VectorSl vec_sl] (vslb, vslh, vslw) }
3003
3004    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3005    pub trait VectorSr<Other> {
3006        type Result;
3007        unsafe fn vec_sr(self, b: Other) -> Self::Result;
3008    }
3009
3010    impl_shift! { vsrb simd_shr u8 }
3011    impl_shift! { vsrh simd_shr u16 }
3012    impl_shift! { vsrw simd_shr u32 }
3013
3014    impl_vec_shift! { [VectorSr vec_sr] (vsrb, vsrh, vsrw) }
3015
3016    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3017    pub trait VectorSra<Other> {
3018        type Result;
3019        unsafe fn vec_sra(self, b: Other) -> Self::Result;
3020    }
3021
3022    impl_vec_shift! { [VectorSra vec_sra] (vsrab, vsrah, vsraw) }
3023
3024    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3025    pub trait VectorSld {
3026        unsafe fn vec_sld<const UIMM4: i32>(self, b: Self) -> Self;
3027        unsafe fn vec_sldw<const UIMM2: i32>(self, b: Self) -> Self;
3028    }
3029
3030    #[inline]
3031    #[target_feature(enable = "altivec")]
3032    #[cfg_attr(test, assert_instr(vsldoi, UIMM4 = 1))]
3033    unsafe fn vsldoi<const UIMM4: i32>(
3034        a: vector_unsigned_char,
3035        b: vector_unsigned_char,
3036    ) -> vector_unsigned_char {
3037        static_assert_uimm_bits!(UIMM4, 4);
3038        let d = UIMM4 as u8;
3039        if cfg!(target_endian = "little") {
3040            let perm = u8x16::new(
3041                16 - d,
3042                17 - d,
3043                18 - d,
3044                19 - d,
3045                20 - d,
3046                21 - d,
3047                22 - d,
3048                23 - d,
3049                24 - d,
3050                25 - d,
3051                26 - d,
3052                27 - d,
3053                28 - d,
3054                29 - d,
3055                30 - d,
3056                31 - d,
3057            );
3058
3059            vec_perm(b, a, transmute(perm))
3060        } else {
3061            let perm = u8x16::new(
3062                d,
3063                d + 1,
3064                d + 2,
3065                d + 3,
3066                d + 4,
3067                d + 5,
3068                d + 6,
3069                d + 7,
3070                d + 8,
3071                d + 9,
3072                d + 10,
3073                d + 11,
3074                d + 12,
3075                d + 13,
3076                d + 14,
3077                d + 15,
3078            );
3079            vec_perm(a, b, transmute(perm))
3080        }
3081    }
3082
3083    // TODO: collapse the two once generic_const_exprs are usable.
3084    #[inline]
3085    #[target_feature(enable = "altivec")]
3086    #[cfg_attr(test, assert_instr(xxsldwi, UIMM2 = 1))]
3087    unsafe fn xxsldwi<const UIMM2: i32>(
3088        a: vector_unsigned_char,
3089        b: vector_unsigned_char,
3090    ) -> vector_unsigned_char {
3091        static_assert_uimm_bits!(UIMM2, 2);
3092        let d = (UIMM2 << 2) as u8;
3093        if cfg!(target_endian = "little") {
3094            let perm = u8x16::new(
3095                16 - d,
3096                17 - d,
3097                18 - d,
3098                19 - d,
3099                20 - d,
3100                21 - d,
3101                22 - d,
3102                23 - d,
3103                24 - d,
3104                25 - d,
3105                26 - d,
3106                27 - d,
3107                28 - d,
3108                29 - d,
3109                30 - d,
3110                31 - d,
3111            );
3112
3113            vec_perm(b, a, transmute(perm))
3114        } else {
3115            let perm = u8x16::new(
3116                d,
3117                d + 1,
3118                d + 2,
3119                d + 3,
3120                d + 4,
3121                d + 5,
3122                d + 6,
3123                d + 7,
3124                d + 8,
3125                d + 9,
3126                d + 10,
3127                d + 11,
3128                d + 12,
3129                d + 13,
3130                d + 14,
3131                d + 15,
3132            );
3133            vec_perm(a, b, transmute(perm))
3134        }
3135    }
3136
3137    macro_rules! impl_vec_sld {
3138        ($($ty:ident),+) => { $(
3139            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3140            impl VectorSld for $ty {
3141                #[inline]
3142                #[target_feature(enable = "altivec")]
3143                unsafe fn vec_sld<const UIMM4: i32>(self, b: Self) -> Self {
3144                    transmute(vsldoi::<UIMM4>(transmute(self), transmute(b)))
3145                }
3146                #[inline]
3147                #[target_feature(enable = "altivec")]
3148                unsafe fn vec_sldw<const UIMM2: i32>(self, b: Self) -> Self {
3149                    transmute(xxsldwi::<UIMM2>(transmute(self), transmute(b)))
3150                }
3151           }
3152        )+ };
3153    }
3154
3155    impl_vec_sld! { vector_bool_char, vector_signed_char, vector_unsigned_char }
3156    impl_vec_sld! { vector_bool_short, vector_signed_short, vector_unsigned_short }
3157    impl_vec_sld! { vector_bool_int, vector_signed_int, vector_unsigned_int }
3158    impl_vec_sld! { vector_float }
3159
3160    macro_rules! impl_vec_shift_long {
3161        ([$Trait:ident $m:ident] ($f:ident)) => {
3162            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
3163            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_char, vector_unsigned_char) -> vector_signed_char }
3164            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_short, vector_unsigned_char) -> vector_unsigned_short }
3165            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_short, vector_unsigned_char) -> vector_signed_short }
3166            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_int, vector_unsigned_char) -> vector_unsigned_int }
3167            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_int, vector_unsigned_char) -> vector_signed_int }
3168        };
3169    }
3170
3171    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3172    pub trait VectorSll<Other> {
3173        type Result;
3174        unsafe fn vec_sll(self, b: Other) -> Self::Result;
3175    }
3176
3177    impl_vec_shift_long! { [VectorSll vec_sll] (vsl) }
3178
3179    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3180    pub trait VectorSrl<Other> {
3181        type Result;
3182        unsafe fn vec_srl(self, b: Other) -> Self::Result;
3183    }
3184
3185    impl_vec_shift_long! { [VectorSrl vec_srl] (vsr) }
3186
3187    macro_rules! impl_vec_shift_octect {
3188        ([$Trait:ident $m:ident] ($f:ident)) => {
3189            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_char, vector_signed_char) -> vector_unsigned_char }
3190            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_char, vector_signed_char) -> vector_signed_char }
3191            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_short, vector_signed_char) -> vector_unsigned_short }
3192            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_short, vector_signed_char) -> vector_signed_short }
3193            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_int, vector_signed_char) -> vector_unsigned_int }
3194            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_int, vector_signed_char) -> vector_signed_int }
3195            impl_vec_trait!{ [$Trait $m]+ $f (vector_float, vector_signed_char) -> vector_float }
3196            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_char, vector_unsigned_char) -> vector_unsigned_char }
3197            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_char, vector_unsigned_char) -> vector_signed_char }
3198            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_short, vector_unsigned_char) -> vector_unsigned_short }
3199            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_short, vector_unsigned_char) -> vector_signed_short }
3200            impl_vec_trait!{ [$Trait $m]+ $f (vector_unsigned_int, vector_unsigned_char) -> vector_unsigned_int }
3201            impl_vec_trait!{ [$Trait $m]+ $f (vector_signed_int, vector_unsigned_char) -> vector_signed_int }
3202            impl_vec_trait!{ [$Trait $m]+ $f (vector_float, vector_unsigned_char) -> vector_float }
3203        };
3204    }
3205
3206    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3207    pub trait VectorSlo<Other> {
3208        type Result;
3209        unsafe fn vec_slo(self, b: Other) -> Self::Result;
3210    }
3211
3212    impl_vec_shift_octect! { [VectorSlo vec_slo] (vslo) }
3213
3214    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3215    pub trait VectorSro<Other> {
3216        type Result;
3217        unsafe fn vec_sro(self, b: Other) -> Self::Result;
3218    }
3219
3220    impl_vec_shift_octect! { [VectorSro vec_sro] (vsro) }
3221
3222    test_impl! { vec_vcntlzb(a: vector_signed_char) -> vector_signed_char [simd_ctlz, vclzb] }
3223    test_impl! { vec_vcntlzh(a: vector_signed_short) -> vector_signed_short [simd_ctlz, vclzh] }
3224    test_impl! { vec_vcntlzw(a: vector_signed_int) -> vector_signed_int [simd_ctlz, vclzw] }
3225
3226    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3227    pub trait VectorCntlz {
3228        unsafe fn vec_cntlz(self) -> Self;
3229    }
3230
3231    macro_rules! impl_vec_cntlz {
3232        ($fun:ident ($a:ty)) => {
3233            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3234            impl VectorCntlz for $a {
3235                #[inline]
3236                #[target_feature(enable = "altivec")]
3237                unsafe fn vec_cntlz(self) -> Self {
3238                    transmute($fun(transmute(self)))
3239                }
3240            }
3241        };
3242    }
3243
3244    impl_vec_cntlz! { vec_vcntlzb(vector_signed_char) }
3245    impl_vec_cntlz! { vec_vcntlzb(vector_unsigned_char) }
3246    impl_vec_cntlz! { vec_vcntlzh(vector_signed_short) }
3247    impl_vec_cntlz! { vec_vcntlzh(vector_unsigned_short) }
3248    impl_vec_cntlz! { vec_vcntlzw(vector_signed_int) }
3249    impl_vec_cntlz! { vec_vcntlzw(vector_unsigned_int) }
3250
3251    macro_rules! impl_vrl {
3252        ($fun:ident $ty:ident) => {
3253            #[inline]
3254            #[target_feature(enable = "altivec")]
3255            #[cfg_attr(test, assert_instr($fun))]
3256            unsafe fn $fun(a: t_t_l!($ty), b: t_t_l!($ty)) -> t_t_l!($ty) {
3257                simd_funnel_shl(a, a, b)
3258            }
3259        };
3260    }
3261
3262    impl_vrl! { vrlb u8 }
3263    impl_vrl! { vrlh u16 }
3264    impl_vrl! { vrlw u32 }
3265
3266    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3267    pub trait VectorRl {
3268        type Shift;
3269        unsafe fn vec_rl(self, b: Self::Shift) -> Self;
3270    }
3271
3272    macro_rules! impl_vec_rl {
3273        ($fun:ident ($a:ident)) => {
3274            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3275            impl VectorRl for $a {
3276                type Shift = t_u!($a);
3277                #[inline]
3278                #[target_feature(enable = "altivec")]
3279                unsafe fn vec_rl(self, b: Self::Shift) -> Self {
3280                    transmute($fun(transmute(self), b))
3281                }
3282            }
3283        };
3284    }
3285
3286    impl_vec_rl! { vrlb(vector_signed_char) }
3287    impl_vec_rl! { vrlh(vector_signed_short) }
3288    impl_vec_rl! { vrlw(vector_signed_int) }
3289    impl_vec_rl! { vrlb(vector_unsigned_char) }
3290    impl_vec_rl! { vrlh(vector_unsigned_short) }
3291    impl_vec_rl! { vrlw(vector_unsigned_int) }
3292
3293    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3294    pub trait VectorRound {
3295        unsafe fn vec_round(self) -> Self;
3296    }
3297
3298    test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] }
3299
3300    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
3301    impl VectorRound for vector_float {
3302        #[inline]
3303        #[target_feature(enable = "altivec")]
3304        unsafe fn vec_round(self) -> Self {
3305            vec_vrfin(self)
3306        }
3307    }
3308}
3309
3310/// Vector Insert
3311///
3312/// ## Purpose
3313/// Returns a copy of vector b with element c replaced by the value of a.
3314///
3315/// ## Result value
3316/// r contains a copy of vector b with element c replaced by the value of a.
3317/// This function uses modular arithmetic on c to determine the element number.
3318/// For example, if c is out of range, the compiler uses c modulo the number of
3319/// elements in the vector to determine the element position.
3320#[inline]
3321#[target_feature(enable = "altivec")]
3322#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3323pub unsafe fn vec_insert<T, const IDX: u32>(a: T, b: <T as sealed::VectorInsert>::Scalar) -> T
3324where
3325    T: sealed::VectorInsert,
3326{
3327    a.vec_insert::<IDX>(b)
3328}
3329
3330/// Vector Extract
3331///
3332/// ## Purpose
3333/// Returns the value of the bth element of vector a.
3334///
3335/// ## Result value
3336/// The value of each element of r is the element of a at position b modulo the number of
3337/// elements of a.
3338#[inline]
3339#[target_feature(enable = "altivec")]
3340#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3341pub unsafe fn vec_extract<T, const IDX: u32>(a: T) -> <T as sealed::VectorExtract>::Scalar
3342where
3343    T: sealed::VectorExtract,
3344{
3345    a.vec_extract::<IDX>()
3346}
3347
3348/// Vector Merge Low
3349#[inline]
3350#[target_feature(enable = "altivec")]
3351#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3352pub unsafe fn vec_mergel<T, U>(a: T, b: U) -> <T as sealed::VectorMergel<U>>::Result
3353where
3354    T: sealed::VectorMergel<U>,
3355{
3356    a.vec_mergel(b)
3357}
3358
3359/// Vector Merge High
3360#[inline]
3361#[target_feature(enable = "altivec")]
3362#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3363pub unsafe fn vec_mergeh<T, U>(a: T, b: U) -> <T as sealed::VectorMergeh<U>>::Result
3364where
3365    T: sealed::VectorMergeh<U>,
3366{
3367    a.vec_mergeh(b)
3368}
3369
3370/// Vector Pack
3371#[inline]
3372#[target_feature(enable = "altivec")]
3373#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3374pub unsafe fn vec_pack<T, U>(a: T, b: U) -> <T as sealed::VectorPack<U>>::Result
3375where
3376    T: sealed::VectorPack<U>,
3377{
3378    a.vec_pack(b)
3379}
3380
3381/// Vector Pack Saturated
3382#[inline]
3383#[target_feature(enable = "altivec")]
3384#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3385pub unsafe fn vec_packs<T, U>(a: T, b: U) -> <T as sealed::VectorPacks<U>>::Result
3386where
3387    T: sealed::VectorPacks<U>,
3388{
3389    a.vec_packs(b)
3390}
3391
3392/// Vector Pack Saturated Unsigned
3393#[inline]
3394#[target_feature(enable = "altivec")]
3395#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3396pub unsafe fn vec_packsu<T, U>(a: T, b: U) -> <T as sealed::VectorPacksu<U>>::Result
3397where
3398    T: sealed::VectorPacksu<U>,
3399{
3400    a.vec_packsu(b)
3401}
3402
3403/// Vector Unpack High
3404#[inline]
3405#[target_feature(enable = "altivec")]
3406#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3407pub unsafe fn vec_unpackh<T>(a: T) -> <T as sealed::VectorUnpackh>::Result
3408where
3409    T: sealed::VectorUnpackh,
3410{
3411    a.vec_unpackh()
3412}
3413
3414/// Vector Unpack Low
3415#[inline]
3416#[target_feature(enable = "altivec")]
3417#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3418pub unsafe fn vec_unpackl<T>(a: T) -> <T as sealed::VectorUnpackl>::Result
3419where
3420    T: sealed::VectorUnpackl,
3421{
3422    a.vec_unpackl()
3423}
3424
3425/// Vector Shift Left
3426#[inline]
3427#[target_feature(enable = "altivec")]
3428#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3429pub unsafe fn vec_sl<T, U>(a: T, b: U) -> <T as sealed::VectorSl<U>>::Result
3430where
3431    T: sealed::VectorSl<U>,
3432{
3433    a.vec_sl(b)
3434}
3435
3436/// Vector Shift Right
3437#[inline]
3438#[target_feature(enable = "altivec")]
3439#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3440pub unsafe fn vec_sr<T, U>(a: T, b: U) -> <T as sealed::VectorSr<U>>::Result
3441where
3442    T: sealed::VectorSr<U>,
3443{
3444    a.vec_sr(b)
3445}
3446
3447/// Vector Shift Right Algebraic
3448#[inline]
3449#[target_feature(enable = "altivec")]
3450#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3451pub unsafe fn vec_sra<T, U>(a: T, b: U) -> <T as sealed::VectorSra<U>>::Result
3452where
3453    T: sealed::VectorSra<U>,
3454{
3455    a.vec_sra(b)
3456}
3457
3458/// Vector Shift Left Double
3459///
3460/// ## Endian considerations
3461///
3462/// This intrinsic is not endian-neutral, so uses of vec_sld in
3463/// big-endian code must be rewritten for little-endian targets.
3464///
3465/// Historically, vec_sld could be used to shift by amounts not a multiple of the element size
3466/// for most types, in which case the purpose of the shift is difficult to determine and difficult
3467/// to automatically rewrite efficiently for little endian.
3468///
3469/// So the concatenation of a and b is done in big-endian fashion (left to right), and the shift is
3470/// always to the left. This will generally produce surprising results for little-endian targets.
3471#[inline]
3472#[target_feature(enable = "altivec")]
3473#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3474pub unsafe fn vec_sld<T, const UIMM4: i32>(a: T, b: T) -> T
3475where
3476    T: sealed::VectorSld,
3477{
3478    a.vec_sld::<UIMM4>(b)
3479}
3480
3481/// Vector Shift Left Double by Words
3482///
3483/// ## Endian considerations
3484///
3485/// This intrinsic is not endian-neutral, so uses of vec_sldw in
3486/// big-endian code must be rewritten for little-endian targets.
3487///
3488/// The concatenation of a and b is done in big-endian fashion (left to right), and the shift is
3489/// always to the left. This will generally produce surprising results for little- endian targets.
3490#[inline]
3491#[target_feature(enable = "altivec")]
3492#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3493pub unsafe fn vec_sldw<T, const UIMM2: i32>(a: T, b: T) -> T
3494where
3495    T: sealed::VectorSld,
3496{
3497    a.vec_sldw::<UIMM2>(b)
3498}
3499
3500/// Vector Shift Left Long
3501///
3502/// ## Endian considerations
3503/// This intrinsic is not endian-neutral, so uses of vec_sll in big-endian
3504/// code must be rewritten for little-endian targets.
3505#[inline]
3506#[target_feature(enable = "altivec")]
3507#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3508pub unsafe fn vec_sll<T, U>(a: T, b: U) -> <T as sealed::VectorSll<U>>::Result
3509where
3510    T: sealed::VectorSll<U>,
3511{
3512    a.vec_sll(b)
3513}
3514
3515/// Vector Shift Right Long
3516///
3517/// ## Endian considerations
3518/// This intrinsic is not endian-neutral, so uses of vec_srl in big-endian
3519/// code must be rewritten for little-endian targets.
3520#[inline]
3521#[target_feature(enable = "altivec")]
3522#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3523pub unsafe fn vec_srl<T, U>(a: T, b: U) -> <T as sealed::VectorSrl<U>>::Result
3524where
3525    T: sealed::VectorSrl<U>,
3526{
3527    a.vec_srl(b)
3528}
3529
3530/// Vector Shift Left by Octets
3531///
3532/// ## Endian considerations
3533/// This intrinsic is not endian-neutral, so uses of vec_slo in big-endian code must be rewritten
3534/// for little-endian targets. The shift count is in element 15 of b for big-endian, but in element
3535/// 0 of b for little-endian.
3536#[inline]
3537#[target_feature(enable = "altivec")]
3538#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3539pub unsafe fn vec_slo<T, U>(a: T, b: U) -> <T as sealed::VectorSlo<U>>::Result
3540where
3541    T: sealed::VectorSlo<U>,
3542{
3543    a.vec_slo(b)
3544}
3545
3546/// Vector Shift Right by Octets
3547///
3548/// ## Endian considerations
3549/// This intrinsic is not endian-neutral, so uses of vec_sro in big-endian code must be rewritten
3550/// for little-endian targets. The shift count is in element 15 of b for big-endian, but in element
3551/// 0 of b for little-endian.
3552#[inline]
3553#[target_feature(enable = "altivec")]
3554#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3555pub unsafe fn vec_sro<T, U>(a: T, b: U) -> <T as sealed::VectorSro<U>>::Result
3556where
3557    T: sealed::VectorSro<U>,
3558{
3559    a.vec_sro(b)
3560}
3561
3562/// Vector Shift Left Variable
3563///
3564/// ## Result value
3565/// Let v be a 17-byte vector formed from a in bytes `[0:15]` and a zero byte in element 16.
3566/// Then each byte element i of r is determined as follows. The start bit sb is
3567/// obtained from bits 5:7 of byte element i of b. Then the contents of bits sb:sb+7 of the
3568/// halfword in byte elements i:i+1 of v are placed into byte element i of r.
3569///
3570/// ## Endian considerations
3571/// All bit and byte element numbers are specified in big-endian order. This intrinsic is not
3572/// endian-neutral.
3573#[inline]
3574#[target_feature(enable = "power9-altivec")]
3575#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3576pub unsafe fn vec_slv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char {
3577    vslv(a, b)
3578}
3579
3580/// Vector Shift Right Variable
3581///
3582/// ## Result value
3583/// Let v be a 17-byte vector formed from a zero byte in element 0 and the elements of
3584/// a in bytes `[1:16]`. Then each byte element i of r is determined as follows. The start bit sb is
3585/// obtained from bits 5:7 of byte element i of b. Then the contents of bits (8 – sb):(15 – sb) of
3586/// the halfword in byte elements i:i+1 of v are placed into byte element i of r.
3587///
3588/// ## Endian considerations
3589/// All bit and byte element numbers are specified in big-endian order. This intrinsic is not
3590/// endian-neutral.
3591#[inline]
3592#[target_feature(enable = "power9-altivec")]
3593#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3594pub unsafe fn vec_srv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char {
3595    vsrv(a, b)
3596}
3597
3598/// Vector Load Indexed.
3599#[inline]
3600#[target_feature(enable = "altivec")]
3601#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3602pub unsafe fn vec_ld<T>(off: isize, p: T) -> <T as sealed::VectorLd>::Result
3603where
3604    T: sealed::VectorLd,
3605{
3606    p.vec_ld(off)
3607}
3608
3609/// Vector Load Indexed Least Recently Used.
3610#[inline]
3611#[target_feature(enable = "altivec")]
3612#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3613pub unsafe fn vec_ldl<T>(off: isize, p: T) -> <T as sealed::VectorLd>::Result
3614where
3615    T: sealed::VectorLd,
3616{
3617    p.vec_ldl(off)
3618}
3619
3620/// Vector Load Element Indexed.
3621#[inline]
3622#[target_feature(enable = "altivec")]
3623#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3624pub unsafe fn vec_lde<T>(off: isize, p: T) -> <T as sealed::VectorLde>::Result
3625where
3626    T: sealed::VectorLde,
3627{
3628    p.vec_lde(off)
3629}
3630
3631/// Vector Store Indexed
3632///
3633/// ## Purpose
3634/// Stores a 16-byte vector into memory at the address specified by a displacement and a
3635/// pointer, ignoring the four low-order bits of the calculated address.
3636///
3637/// ## Operation
3638/// A memory address is obtained by adding b and c, and masking off the four low-order
3639/// bits of the result. The 16-byte vector in a is stored to the resultant memory address.
3640#[inline]
3641#[target_feature(enable = "altivec")]
3642#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3643pub unsafe fn vec_st<T>(a: T, off: isize, c: <T as sealed::VectorSt>::Target)
3644where
3645    T: sealed::VectorSt,
3646{
3647    a.vec_st(off, c)
3648}
3649
3650/// Vector Store Indexed Least Recently Used
3651///
3652/// ## Purpose
3653/// Stores a 16-byte vector into memory at the address specified by a displacement and
3654/// a pointer, ignoring the four low-order bits of the calculated address, and marking the cache
3655/// line containing the address as least frequently used.
3656///
3657/// ## Operation
3658/// A memory address is obtained by adding b and c, and masking off the four
3659/// low-order bits of the result. The 16-byte vector in a is stored to the resultant memory
3660/// address, and the containing cache line is marked as least frequently used.
3661///
3662/// ## Notes
3663/// This intrinsic can be used to indicate the last access to a portion of memory, as a hint to the
3664/// data cache controller that the associated cache line can be replaced without performance loss.
3665#[inline]
3666#[target_feature(enable = "altivec")]
3667#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3668pub unsafe fn vec_stl<T>(a: T, off: isize, c: <T as sealed::VectorSt>::Target)
3669where
3670    T: sealed::VectorSt,
3671{
3672    a.vec_stl(off, c)
3673}
3674
3675/// Vector Store Element Indexed
3676///
3677/// ## Purpose
3678/// Stores a single element from a 16-byte vector into memory at the address specified by
3679/// a displacement and a pointer, aligned to the element size.
3680///
3681/// ## Operation
3682/// The integer value b is added to the pointer value c. The resulting address is
3683/// rounded down to the nearest address that is a multiple of es, where es is 1 for char pointers,
3684/// 2 for short pointers, and 4 for float or int pointers. An element offset eo is calculated by
3685/// taking the resultant address modulo 16. The vector element of a at offset eo is stored to the
3686/// resultant address.
3687///
3688/// ## Notes
3689/// Be careful to note that the address (b+c) is aligned to an element boundary. Do not attempt
3690/// to store unaligned data with this intrinsic.
3691#[inline]
3692#[target_feature(enable = "altivec")]
3693#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3694pub unsafe fn vec_ste<T>(a: T, off: isize, c: <T as sealed::VectorSte>::Target)
3695where
3696    T: sealed::VectorSte,
3697{
3698    a.vec_ste(off, c)
3699}
3700
3701/// VSX Unaligned Load
3702#[inline]
3703#[target_feature(enable = "altivec")]
3704#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3705pub unsafe fn vec_xl<T>(off: isize, p: T) -> <T as sealed::VectorXl>::Result
3706where
3707    T: sealed::VectorXl,
3708{
3709    p.vec_xl(off)
3710}
3711
3712/// VSX Unaligned Store
3713#[inline]
3714#[target_feature(enable = "altivec")]
3715#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3716pub unsafe fn vec_xst<T>(v: T, off: isize, p: <T as sealed::VectorXst>::Out)
3717where
3718    T: sealed::VectorXst,
3719{
3720    v.vec_xst(off, p)
3721}
3722
3723/// Vector Base-2 Logarithm Estimate
3724#[inline]
3725#[target_feature(enable = "altivec")]
3726#[cfg_attr(test, assert_instr(vlogefp))]
3727#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3728pub unsafe fn vec_loge(a: vector_float) -> vector_float {
3729    vlogefp(a)
3730}
3731
3732/// Vector floor.
3733#[inline]
3734#[target_feature(enable = "altivec")]
3735#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3736pub unsafe fn vec_floor(a: vector_float) -> vector_float {
3737    sealed::vec_floor(a)
3738}
3739
3740/// Vector expte.
3741#[inline]
3742#[target_feature(enable = "altivec")]
3743#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3744pub unsafe fn vec_expte(a: vector_float) -> vector_float {
3745    sealed::vec_vexptefp(a)
3746}
3747
3748/// Vector cmplt.
3749#[inline]
3750#[target_feature(enable = "altivec")]
3751#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3752pub unsafe fn vec_cmplt<T, U>(a: U, b: T) -> <T as sealed::VectorCmpGt<U>>::Result
3753where
3754    T: sealed::VectorCmpGt<U>,
3755{
3756    vec_cmpgt(b, a)
3757}
3758
3759/// Vector cmple.
3760#[inline]
3761#[target_feature(enable = "altivec")]
3762#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3763pub unsafe fn vec_cmple(a: vector_float, b: vector_float) -> vector_bool_int {
3764    vec_cmpge(b, a)
3765}
3766
3767/// Vector cmpgt.
3768#[inline]
3769#[target_feature(enable = "altivec")]
3770#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3771pub unsafe fn vec_cmpgt<T, U>(a: T, b: U) -> <T as sealed::VectorCmpGt<U>>::Result
3772where
3773    T: sealed::VectorCmpGt<U>,
3774{
3775    a.vec_cmpgt(b)
3776}
3777
3778/// Vector cmpge.
3779#[inline]
3780#[target_feature(enable = "altivec")]
3781#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3782pub unsafe fn vec_cmpge(a: vector_float, b: vector_float) -> vector_bool_int {
3783    sealed::vec_vcmpgefp(a, b)
3784}
3785
3786/// Vector cmpeq.
3787#[inline]
3788#[target_feature(enable = "altivec")]
3789#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3790pub unsafe fn vec_cmpeq<T, U>(a: T, b: U) -> <T as sealed::VectorCmpEq<U>>::Result
3791where
3792    T: sealed::VectorCmpEq<U>,
3793{
3794    a.vec_cmpeq(b)
3795}
3796
3797/// Vector Compare Not Equal
3798///
3799/// ## Result value
3800/// For each element of r, the value of each bit is 1 if the corresponding elements
3801/// of a and b are not equal. Otherwise, the value of each bit is 0.
3802#[inline]
3803#[target_feature(enable = "altivec")]
3804#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3805pub unsafe fn vec_cmpne<T, U>(a: T, b: U) -> <T as sealed::VectorCmpNe<U>>::Result
3806where
3807    T: sealed::VectorCmpNe<U>,
3808{
3809    a.vec_cmpne(b)
3810}
3811
3812/// Vector cmpb.
3813#[inline]
3814#[target_feature(enable = "altivec")]
3815#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3816pub unsafe fn vec_cmpb(a: vector_float, b: vector_float) -> vector_signed_int {
3817    sealed::vec_vcmpbfp(a, b)
3818}
3819
3820/// Vector ceil.
3821#[inline]
3822#[target_feature(enable = "altivec")]
3823#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3824pub unsafe fn vec_ceil(a: vector_float) -> vector_float {
3825    sealed::vec_vceil(a)
3826}
3827
3828/// Vector avg.
3829#[inline]
3830#[target_feature(enable = "altivec")]
3831#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3832pub unsafe fn vec_avg<T, U>(a: T, b: U) -> <T as sealed::VectorAvg<U>>::Result
3833where
3834    T: sealed::VectorAvg<U>,
3835{
3836    a.vec_avg(b)
3837}
3838
3839/// Vector andc.
3840#[inline]
3841#[target_feature(enable = "altivec")]
3842#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3843pub unsafe fn vec_andc<T, U>(a: T, b: U) -> <T as sealed::VectorAndc<U>>::Result
3844where
3845    T: sealed::VectorAndc<U>,
3846{
3847    a.vec_andc(b)
3848}
3849
3850/// Vector OR with Complement
3851///
3852/// ## Purpose
3853/// Performs a bitwise OR of the first vector with the bitwise-complemented second vector.
3854///
3855/// ## Result value
3856/// r is the bitwise OR of a and the bitwise complement of b.
3857#[inline]
3858#[target_feature(enable = "altivec")]
3859#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3860pub unsafe fn vec_orc<T, U>(a: T, b: U) -> <T as sealed::VectorOrc<U>>::Result
3861where
3862    T: sealed::VectorOrc<U>,
3863{
3864    a.vec_orc(b)
3865}
3866
3867/// Vector and.
3868#[inline]
3869#[target_feature(enable = "altivec")]
3870#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3871pub unsafe fn vec_and<T, U>(a: T, b: U) -> <T as sealed::VectorAnd<U>>::Result
3872where
3873    T: sealed::VectorAnd<U>,
3874{
3875    a.vec_and(b)
3876}
3877
3878/// Vector or.
3879#[inline]
3880#[target_feature(enable = "altivec")]
3881#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3882pub unsafe fn vec_or<T, U>(a: T, b: U) -> <T as sealed::VectorOr<U>>::Result
3883where
3884    T: sealed::VectorOr<U>,
3885{
3886    a.vec_or(b)
3887}
3888
3889/// Vector NAND
3890///
3891/// ## Purpose
3892/// Performs a bitwise NAND of two vectors.
3893///
3894/// ## Result value
3895/// r is the bitwise NAND of a and b.
3896#[inline]
3897#[target_feature(enable = "altivec")]
3898#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3899pub unsafe fn vec_nand<T, U>(a: T, b: U) -> <T as sealed::VectorNand<U>>::Result
3900where
3901    T: sealed::VectorNand<U>,
3902{
3903    a.vec_nand(b)
3904}
3905
3906/// Vector nor.
3907#[inline]
3908#[target_feature(enable = "altivec")]
3909#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3910pub unsafe fn vec_nor<T, U>(a: T, b: U) -> <T as sealed::VectorNor<U>>::Result
3911where
3912    T: sealed::VectorNor<U>,
3913{
3914    a.vec_nor(b)
3915}
3916
3917/// Vector xor.
3918#[inline]
3919#[target_feature(enable = "altivec")]
3920#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3921pub unsafe fn vec_xor<T, U>(a: T, b: U) -> <T as sealed::VectorXor<U>>::Result
3922where
3923    T: sealed::VectorXor<U>,
3924{
3925    a.vec_xor(b)
3926}
3927
3928/// Vector adds.
3929#[inline]
3930#[target_feature(enable = "altivec")]
3931#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3932pub unsafe fn vec_adds<T, U>(a: T, b: U) -> <T as sealed::VectorAdds<U>>::Result
3933where
3934    T: sealed::VectorAdds<U>,
3935{
3936    a.vec_adds(b)
3937}
3938
3939/// Vector addc.
3940#[inline]
3941#[target_feature(enable = "altivec")]
3942#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3943pub unsafe fn vec_addc(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int {
3944    sealed::vec_vaddcuw(a, b)
3945}
3946
3947/// Vector abs.
3948#[inline]
3949#[target_feature(enable = "altivec")]
3950#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3951pub unsafe fn vec_abs<T>(a: T) -> T
3952where
3953    T: sealed::VectorAbs,
3954{
3955    a.vec_abs()
3956}
3957
3958/// Vector abss.
3959#[inline]
3960#[target_feature(enable = "altivec")]
3961#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3962pub unsafe fn vec_abss<T>(a: T) -> T
3963where
3964    T: sealed::VectorAbss,
3965{
3966    a.vec_abss()
3967}
3968
3969/// Vector Rotate Left
3970///
3971/// ## Purpose
3972/// Rotates each element of a vector left by a given number of bits.
3973///
3974/// ## Result value
3975/// Each element of r is obtained by rotating the corresponding element of a left by
3976/// the number of bits specified by the corresponding element of b.
3977#[inline]
3978#[target_feature(enable = "altivec")]
3979#[unstable(feature = "stdarch_powerpc", issue = "111145")]
3980pub unsafe fn vec_rl<T>(a: T, b: <T as sealed::VectorRl>::Shift) -> T
3981where
3982    T: sealed::VectorRl,
3983{
3984    a.vec_rl(b)
3985}
3986
3987/// Vector Round
3988///
3989/// ## Purpose
3990/// Returns a vector containing the rounded values of the corresponding elements of the
3991/// source vector.
3992///
3993/// ## Result value
3994/// Each element of r contains the value of the corresponding element of a, rounded
3995/// to the nearest representable floating-point integer, using IEEE round-to-nearest
3996/// rounding.
3997/// The current floating-point rounding mode is ignored.
3998#[inline]
3999#[target_feature(enable = "altivec")]
4000#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4001pub unsafe fn vec_round<T>(a: T) -> T
4002where
4003    T: sealed::VectorRound,
4004{
4005    a.vec_round()
4006}
4007
4008/// Vector Splat
4009#[inline]
4010#[target_feature(enable = "altivec")]
4011#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4012pub unsafe fn vec_splat<T, const IMM: u32>(a: T) -> T
4013where
4014    T: sealed::VectorSplat,
4015{
4016    a.vec_splat::<IMM>()
4017}
4018
4019splat! { vec_splat_u8, u8, u8x16 [vspltisb / xxspltib, "Vector Splat to Unsigned Byte"] }
4020splat! { vec_splat_s8, i8, i8x16 [vspltisb / xxspltib, "Vector Splat to Signed Byte"] }
4021splat! { vec_splat_u16, u16, u16x8 [vspltish, "Vector Splat to Unsigned Halfword"] }
4022splat! { vec_splat_s16, i16, i16x8 [vspltish, "Vector Splat to Signed Halfword"] }
4023splat! { vec_splat_u32, u32, u32x4 [vspltisw, "Vector Splat to Unsigned Word"] }
4024splat! { vec_splat_s32, i32, i32x4 [vspltisw, "Vector Splat to Signed Word"] }
4025
4026/// Vector splats.
4027#[inline]
4028#[target_feature(enable = "altivec")]
4029#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4030pub unsafe fn vec_splats<T>(a: T) -> <T as sealed::VectorSplats>::Result
4031where
4032    T: sealed::VectorSplats,
4033{
4034    a.vec_splats()
4035}
4036
4037/// Vector sub.
4038#[inline]
4039#[target_feature(enable = "altivec")]
4040#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4041pub unsafe fn vec_sub<T, U>(a: T, b: U) -> <T as sealed::VectorSub<U>>::Result
4042where
4043    T: sealed::VectorSub<U>,
4044{
4045    a.vec_sub(b)
4046}
4047
4048/// Vector Subtract Carryout
4049///
4050/// ## Purpose
4051/// Returns a vector wherein each element contains the carry produced by subtracting the
4052/// corresponding elements of the two source vectors.
4053///
4054/// ## Result value
4055/// The value of each element of r is the complement of the carry produced by subtract- ing the
4056/// value of the corresponding element of b from the value of the corresponding element of a. The
4057/// value is 0 if a borrow occurred, or 1 if no borrow occurred.
4058#[inline]
4059#[target_feature(enable = "altivec")]
4060#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4061pub unsafe fn vec_subc<T, U>(a: T, b: U) -> <T as sealed::VectorSubc<U>>::Result
4062where
4063    T: sealed::VectorSubc<U>,
4064{
4065    a.vec_subc(b)
4066}
4067
4068/// Vector subs.
4069#[inline]
4070#[target_feature(enable = "altivec")]
4071#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4072pub unsafe fn vec_subs<T, U>(a: T, b: U) -> <T as sealed::VectorSubs<U>>::Result
4073where
4074    T: sealed::VectorSubs<U>,
4075{
4076    a.vec_subs(b)
4077}
4078
4079/// Vector min.
4080#[inline]
4081#[target_feature(enable = "altivec")]
4082#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4083pub unsafe fn vec_min<T, U>(a: T, b: U) -> <T as sealed::VectorMin<U>>::Result
4084where
4085    T: sealed::VectorMin<U>,
4086{
4087    a.vec_min(b)
4088}
4089
4090/// Vector max.
4091#[inline]
4092#[target_feature(enable = "altivec")]
4093#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4094pub unsafe fn vec_max<T, U>(a: T, b: U) -> <T as sealed::VectorMax<U>>::Result
4095where
4096    T: sealed::VectorMax<U>,
4097{
4098    a.vec_max(b)
4099}
4100
4101/// Move From Vector Status and Control Register.
4102#[inline]
4103#[target_feature(enable = "altivec")]
4104#[cfg_attr(test, assert_instr(mfvscr))]
4105#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4106pub unsafe fn vec_mfvscr() -> vector_unsigned_short {
4107    mfvscr()
4108}
4109
4110/// Vector Negate
4111#[inline]
4112#[target_feature(enable = "altivec")]
4113#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4114pub unsafe fn vec_neg<T: sealed::VectorNeg>(a: T) -> T {
4115    a.vec_neg()
4116}
4117
4118/// Vector add.
4119#[inline]
4120#[target_feature(enable = "altivec")]
4121#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4122pub unsafe fn vec_add<T, U>(a: T, b: U) -> <T as sealed::VectorAdd<U>>::Result
4123where
4124    T: sealed::VectorAdd<U>,
4125{
4126    a.vec_add(b)
4127}
4128
4129/// Vector Add Extended
4130///
4131/// ## Result value
4132/// The value of each element of r is produced by adding the corresponding elements of
4133/// a and b with a carry specified in the corresponding element of c (1 if there is a carry, 0
4134/// otherwise).
4135#[inline]
4136#[target_feature(enable = "altivec")]
4137#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4138pub unsafe fn vec_adde<T>(a: T, b: T, c: T) -> T
4139where
4140    T: sealed::VectorAdde,
4141{
4142    a.vec_adde(b, c)
4143}
4144
4145/// Vector Convert to Floating-Point
4146#[inline]
4147#[target_feature(enable = "altivec")]
4148#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4149pub unsafe fn vec_ctf<const IMM5: i32, T>(a: T) -> vector_float
4150where
4151    T: sealed::VectorCtf,
4152{
4153    a.vec_ctf::<IMM5>()
4154}
4155
4156/// Vector Convert to Signed Integer
4157#[inline]
4158#[target_feature(enable = "altivec")]
4159#[cfg_attr(test, assert_instr(vctsxs, IMM5 = 1))]
4160#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4161pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
4162    static_assert_uimm_bits!(IMM5, 5);
4163
4164    vctsxs(a, IMM5)
4165}
4166
4167/// Vector Convert to Unsigned Integer
4168#[inline]
4169#[target_feature(enable = "altivec")]
4170#[cfg_attr(test, assert_instr(vctuxs, IMM5 = 1))]
4171#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4172pub unsafe fn vec_ctu<const IMM5: i32>(a: vector_float) -> vector_unsigned_int {
4173    static_assert_uimm_bits!(IMM5, 5);
4174
4175    vctuxs(a, IMM5)
4176}
4177
4178/// Endian-biased intrinsics
4179#[cfg(target_endian = "little")]
4180mod endian {
4181    use super::*;
4182    /// Vector permute.
4183    #[inline]
4184    #[target_feature(enable = "altivec")]
4185    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4186    pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
4187    where
4188        T: sealed::VectorPerm,
4189    {
4190        // vperm has big-endian bias
4191        //
4192        // Xor the mask and flip the arguments
4193        let d = transmute(u8x16::new(
4194            255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
4195        ));
4196        let c = simd_xor(c, d);
4197
4198        b.vec_vperm(a, c)
4199    }
4200
4201    /// Vector Sum Across Partial (1/2) Saturated
4202    #[inline]
4203    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4204    #[target_feature(enable = "altivec")]
4205    pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
4206        // vsum2sws has big-endian bias
4207        //
4208        // swap the even b elements with the odd ones
4209        let flip = transmute(u8x16::new(
4210            4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11,
4211        ));
4212        let b = vec_perm(b, b, flip);
4213        let c = vsum2sws(a, b);
4214
4215        vec_perm(c, c, flip)
4216    }
4217
4218    // Even and Odd are swapped in little-endian
4219    /// Vector Multiply Even
4220    #[inline]
4221    #[target_feature(enable = "altivec")]
4222    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4223    pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
4224    where
4225        T: sealed::VectorMulo<U>,
4226    {
4227        a.vec_mulo(b)
4228    }
4229    /// Vector Multiply Odd
4230    #[inline]
4231    #[target_feature(enable = "altivec")]
4232    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4233    pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
4234    where
4235        T: sealed::VectorMule<U>,
4236    {
4237        a.vec_mule(b)
4238    }
4239}
4240
4241/// Vector Multiply
4242///
4243/// ## Purpose
4244/// Compute the products of corresponding elements of two vectors.
4245///
4246/// ## Result value
4247/// Each element of r receives the product of the corresponding elements of a and b.
4248#[inline]
4249#[target_feature(enable = "altivec")]
4250#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4251pub unsafe fn vec_mul<T>(a: T, b: T) -> T
4252where
4253    T: sealed::VectorMul,
4254{
4255    a.vec_mul(b)
4256}
4257
4258/// Vector Multiply Add Saturated
4259#[inline]
4260#[target_feature(enable = "altivec")]
4261#[cfg_attr(test, assert_instr(vmhaddshs))]
4262#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4263pub unsafe fn vec_madds(
4264    a: vector_signed_short,
4265    b: vector_signed_short,
4266    c: vector_signed_short,
4267) -> vector_signed_short {
4268    vmhaddshs(a, b, c)
4269}
4270
4271/// Vector Multiply Low and Add Unsigned Half Word
4272#[inline]
4273#[target_feature(enable = "altivec")]
4274#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4275pub unsafe fn vec_mladd<T, U>(a: T, b: U, c: U) -> <T as sealed::VectorMladd<U>>::Result
4276where
4277    T: sealed::VectorMladd<U>,
4278{
4279    a.vec_mladd(b, c)
4280}
4281
4282/// Vector Multiply Round and Add Saturated
4283#[inline]
4284#[target_feature(enable = "altivec")]
4285#[cfg_attr(test, assert_instr(vmhraddshs))]
4286#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4287pub unsafe fn vec_mradds(
4288    a: vector_signed_short,
4289    b: vector_signed_short,
4290    c: vector_signed_short,
4291) -> vector_signed_short {
4292    vmhraddshs(a, b, c)
4293}
4294
4295/// Vector Multiply Sum
4296#[inline]
4297#[target_feature(enable = "altivec")]
4298#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4299pub unsafe fn vec_msum<T, B, U>(a: T, b: B, c: U) -> U
4300where
4301    T: sealed::VectorMsum<B, U>,
4302{
4303    a.vec_msum(b, c)
4304}
4305
4306/// Vector Multiply Sum Saturated
4307#[inline]
4308#[target_feature(enable = "altivec")]
4309#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4310pub unsafe fn vec_msums<T, U>(a: T, b: T, c: U) -> U
4311where
4312    T: sealed::VectorMsums<U>,
4313{
4314    a.vec_msums(b, c)
4315}
4316
4317/// Vector Multiply Add
4318#[inline]
4319#[target_feature(enable = "altivec")]
4320#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4321pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
4322    sealed::vec_vmaddfp(a, b, c)
4323}
4324
4325/// Vector Negative Multiply Subtract
4326#[inline]
4327#[target_feature(enable = "altivec")]
4328#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4329pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
4330    sealed::vec_vnmsubfp(a, b, c)
4331}
4332
4333/// Vector Select
4334///
4335/// ## Purpose
4336/// Returns a vector selecting bits from two source vectors depending on the corresponding
4337/// bit values of a third source vector.
4338///
4339/// ## Result value
4340/// Each bit of r has the value of the corresponding bit of a if the corresponding
4341/// bit of c is 0. Otherwise, the bit of r has the value of the corresponding bit of b.
4342#[inline]
4343#[target_feature(enable = "altivec")]
4344#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4345pub unsafe fn vec_sel<T, U>(a: T, b: T, c: U) -> T
4346where
4347    T: sealed::VectorSel<U>,
4348{
4349    a.vec_sel(b, c)
4350}
4351
4352/// Vector Sum Across Partial (1/4) Saturated
4353#[inline]
4354#[target_feature(enable = "altivec")]
4355#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4356pub unsafe fn vec_sum4s<T, U>(a: T, b: U) -> U
4357where
4358    T: sealed::VectorSum4s<U>,
4359{
4360    a.vec_sum4s(b)
4361}
4362
4363/// Vector All Elements Equal
4364#[inline]
4365#[target_feature(enable = "altivec")]
4366#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4367pub unsafe fn vec_all_eq<T, U>(a: T, b: U) -> <T as sealed::VectorAllEq<U>>::Result
4368where
4369    T: sealed::VectorAllEq<U>,
4370{
4371    a.vec_all_eq(b)
4372}
4373
4374/// Vector All Elements Equal
4375#[inline]
4376#[target_feature(enable = "altivec")]
4377#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4378pub unsafe fn vec_any_eq<T, U>(a: T, b: U) -> <T as sealed::VectorAnyEq<U>>::Result
4379where
4380    T: sealed::VectorAnyEq<U>,
4381{
4382    a.vec_any_eq(b)
4383}
4384
4385/// Vector All Elements Greater or Equal
4386#[inline]
4387#[target_feature(enable = "altivec")]
4388#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4389pub unsafe fn vec_all_ge<T, U>(a: T, b: U) -> <T as sealed::VectorAllGe<U>>::Result
4390where
4391    T: sealed::VectorAllGe<U>,
4392{
4393    a.vec_all_ge(b)
4394}
4395
4396/// Vector Any Element Greater or Equal
4397#[inline]
4398#[target_feature(enable = "altivec")]
4399#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4400pub unsafe fn vec_any_ge<T, U>(a: T, b: U) -> <T as sealed::VectorAnyGe<U>>::Result
4401where
4402    T: sealed::VectorAnyGe<U>,
4403{
4404    a.vec_any_ge(b)
4405}
4406
4407/// Vector All Elements Greater Than
4408#[inline]
4409#[target_feature(enable = "altivec")]
4410#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4411pub unsafe fn vec_all_gt<T, U>(a: T, b: U) -> <T as sealed::VectorAllGt<U>>::Result
4412where
4413    T: sealed::VectorAllGt<U>,
4414{
4415    a.vec_all_gt(b)
4416}
4417
4418/// Vector Any Element Greater Than
4419#[inline]
4420#[target_feature(enable = "altivec")]
4421#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4422pub unsafe fn vec_any_gt<T, U>(a: T, b: U) -> <T as sealed::VectorAnyGt<U>>::Result
4423where
4424    T: sealed::VectorAnyGt<U>,
4425{
4426    a.vec_any_gt(b)
4427}
4428
4429/// Vector All In
4430#[inline]
4431#[target_feature(enable = "altivec")]
4432#[cfg_attr(test, assert_instr("vcmpbfp."))]
4433#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4434pub unsafe fn vec_all_in(a: vector_float, b: vector_float) -> bool {
4435    vcmpbfp_p(0, a, b) != 0
4436}
4437
4438/// Vector All Elements Less Than or Equal
4439#[inline]
4440#[target_feature(enable = "altivec")]
4441#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4442pub unsafe fn vec_all_le<T, U>(a: U, b: T) -> <T as sealed::VectorAllGe<U>>::Result
4443where
4444    T: sealed::VectorAllGe<U>,
4445{
4446    b.vec_all_ge(a)
4447}
4448
4449/// Vector Any Element Less Than or Equal
4450#[inline]
4451#[target_feature(enable = "altivec")]
4452#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4453pub unsafe fn vec_any_le<T, U>(a: U, b: T) -> <T as sealed::VectorAnyGe<U>>::Result
4454where
4455    T: sealed::VectorAnyGe<U>,
4456{
4457    b.vec_any_ge(a)
4458}
4459
4460/// Vector All Elements Less Than
4461#[inline]
4462#[target_feature(enable = "altivec")]
4463#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4464pub unsafe fn vec_all_lt<T, U>(a: U, b: T) -> <T as sealed::VectorAllGt<U>>::Result
4465where
4466    T: sealed::VectorAllGt<U>,
4467{
4468    b.vec_all_gt(a)
4469}
4470
4471/// Vector Any Element Less Than
4472#[inline]
4473#[target_feature(enable = "altivec")]
4474#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4475pub unsafe fn vec_any_lt<T, U>(a: U, b: T) -> <T as sealed::VectorAnyGt<U>>::Result
4476where
4477    T: sealed::VectorAnyGt<U>,
4478{
4479    b.vec_any_gt(a)
4480}
4481
4482/// All Elements Not a Number
4483#[inline]
4484#[target_feature(enable = "altivec")]
4485#[cfg_attr(test, assert_instr("vcmpeqfp."))]
4486#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4487pub unsafe fn vec_all_nan(a: vector_float) -> bool {
4488    vcmpeqfp_p(0, a, a) != 0
4489}
4490
4491/// Any Elements Not a Number
4492#[inline]
4493#[target_feature(enable = "altivec")]
4494#[cfg_attr(test, assert_instr("vcmpeqfp."))]
4495#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4496pub unsafe fn vec_any_nan(a: vector_float) -> bool {
4497    vcmpeqfp_p(3, a, a) != 0
4498}
4499
4500/// Vector All Elements Not Equal
4501#[inline]
4502#[target_feature(enable = "altivec")]
4503#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4504pub unsafe fn vec_all_ne<T, U>(a: T, b: U) -> <T as sealed::VectorAllNe<U>>::Result
4505where
4506    T: sealed::VectorAllNe<U>,
4507{
4508    a.vec_all_ne(b)
4509}
4510
4511/// Vector Any Elements Not Equal
4512#[inline]
4513#[target_feature(enable = "altivec")]
4514#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4515pub unsafe fn vec_any_ne<T, U>(a: T, b: U) -> <T as sealed::VectorAnyNe<U>>::Result
4516where
4517    T: sealed::VectorAnyNe<U>,
4518{
4519    a.vec_any_ne(b)
4520}
4521
4522/// All Elements Not Greater Than or Equal
4523#[inline]
4524#[target_feature(enable = "altivec")]
4525#[cfg_attr(test, assert_instr("vcmpgefp."))]
4526#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4527pub unsafe fn vec_all_nge(a: vector_float, b: vector_float) -> bool {
4528    vcmpgefp_p(0, a, b) != 0
4529}
4530
4531/// All Elements Not Greater Than
4532#[inline]
4533#[target_feature(enable = "altivec")]
4534#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4535#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4536pub unsafe fn vec_all_ngt(a: vector_float, b: vector_float) -> bool {
4537    vcmpgtfp_p(0, a, b) != 0
4538}
4539
4540/// All Elements Not Less Than or Equal
4541#[inline]
4542#[target_feature(enable = "altivec")]
4543#[cfg_attr(test, assert_instr("vcmpgefp."))]
4544#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4545pub unsafe fn vec_all_nle(a: vector_float, b: vector_float) -> bool {
4546    vcmpgefp_p(0, b, a) != 0
4547}
4548
4549/// All Elements Not Less Than
4550#[inline]
4551#[target_feature(enable = "altivec")]
4552#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4553#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4554pub unsafe fn vec_all_nlt(a: vector_float, b: vector_float) -> bool {
4555    vcmpgtfp_p(0, b, a) != 0
4556}
4557
4558/// All Elements Numeric
4559#[inline]
4560#[target_feature(enable = "altivec")]
4561#[cfg_attr(test, assert_instr("vcmpgefp."))]
4562#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4563pub unsafe fn vec_all_numeric(a: vector_float) -> bool {
4564    vcmpgefp_p(2, a, a) != 0
4565}
4566
4567/// Any Elements Not Greater Than or Equal
4568#[inline]
4569#[target_feature(enable = "altivec")]
4570#[cfg_attr(test, assert_instr("vcmpgefp."))]
4571#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4572pub unsafe fn vec_any_nge(a: vector_float, b: vector_float) -> bool {
4573    vcmpgefp_p(3, a, b) != 0
4574}
4575
4576/// Any Elements Not Greater Than
4577#[inline]
4578#[target_feature(enable = "altivec")]
4579#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4580#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4581pub unsafe fn vec_any_ngt(a: vector_float, b: vector_float) -> bool {
4582    vcmpgtfp_p(3, a, b) != 0
4583}
4584
4585/// Any Elements Not Less Than or Equal
4586#[inline]
4587#[target_feature(enable = "altivec")]
4588#[cfg_attr(test, assert_instr("vcmpgefp."))]
4589#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4590pub unsafe fn vec_any_nle(a: vector_float, b: vector_float) -> bool {
4591    vcmpgefp_p(3, b, a) != 0
4592}
4593
4594/// Any Elements Not Less Than
4595#[inline]
4596#[target_feature(enable = "altivec")]
4597#[cfg_attr(test, assert_instr("vcmpgtfp."))]
4598#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4599pub unsafe fn vec_any_nlt(a: vector_float, b: vector_float) -> bool {
4600    vcmpgtfp_p(3, b, a) != 0
4601}
4602
4603/// Any Elements Numeric
4604#[inline]
4605#[target_feature(enable = "altivec")]
4606#[cfg_attr(test, assert_instr("vcmpgefp."))]
4607#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4608pub unsafe fn vec_any_numeric(a: vector_float) -> bool {
4609    vcmpgefp_p(1, a, a) != 0
4610}
4611
4612/// Vector Count Leading Zeros
4613///
4614/// ## Purpose
4615/// Returns a vector containing the number of most-significant bits equal to zero of each
4616/// corresponding element of the source vector.
4617///
4618/// ## Result value
4619/// The value of each element of r is set to the number of leading zeros of the
4620/// corresponding element of a.
4621#[inline]
4622#[target_feature(enable = "altivec")]
4623#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4624pub unsafe fn vec_cntlz<T>(a: T) -> T
4625where
4626    T: sealed::VectorCntlz,
4627{
4628    a.vec_cntlz()
4629}
4630
4631/// Any Element Out of Bounds
4632#[inline]
4633#[target_feature(enable = "altivec")]
4634#[cfg_attr(test, assert_instr("vcmpeqfp."))]
4635#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4636pub unsafe fn vec_any_out(a: vector_float) -> bool {
4637    vcmpeqfp_p(1, a, a) != 0
4638}
4639
4640#[cfg(target_endian = "big")]
4641mod endian {
4642    use super::*;
4643    /// Vector permute.
4644    #[inline]
4645    #[target_feature(enable = "altivec")]
4646    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4647    pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
4648    where
4649        T: sealed::VectorPerm,
4650    {
4651        a.vec_vperm(b, c)
4652    }
4653
4654    /// Vector Sum Across Partial (1/2) Saturated
4655    #[inline]
4656    #[target_feature(enable = "altivec")]
4657    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4658    pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
4659        vsum2sws(a, b)
4660    }
4661
4662    /// Vector Multiply Even
4663    #[inline]
4664    #[target_feature(enable = "altivec")]
4665    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4666    pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
4667    where
4668        T: sealed::VectorMule<U>,
4669    {
4670        a.vec_mule(b)
4671    }
4672    /// Vector Multiply Odd
4673    #[inline]
4674    #[target_feature(enable = "altivec")]
4675    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
4676    pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
4677    where
4678        T: sealed::VectorMulo<U>,
4679    {
4680        a.vec_mulo(b)
4681    }
4682}
4683
4684#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4685pub use self::endian::*;
4686
4687#[cfg(test)]
4688mod tests {
4689    use super::*;
4690
4691    use std::mem::transmute;
4692
4693    use crate::core_arch::simd::*;
4694    use stdarch_test::simd_test;
4695
4696    macro_rules! test_vec_2 {
4697        { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
4698            test_vec_2! { $name, $fn, $ty -> $ty, [$($a),+], [$($b),+], [$($d),+] }
4699        };
4700        { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
4701            #[simd_test(enable = "altivec")]
4702            fn $name() {
4703                let a: s_t_l!($ty) = $ty::new($($a),+).into();
4704                let b: s_t_l!($ty) = $ty::new($($b),+).into();
4705
4706                let d = $ty_out::new($($d),+);
4707                let r = $ty_out::from(unsafe { $fn(a, b) });
4708                assert_eq!(d, r);
4709            }
4710         };
4711         { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
4712            #[simd_test(enable = "altivec")]
4713            fn $name() {
4714                let a: s_t_l!($ty) = $ty::new($($a),+).into();
4715                let b: s_t_l!($ty) = $ty::new($($b),+).into();
4716
4717                let r = $ty_out::from(unsafe { $fn(a, b) });
4718                assert_eq!($d, r);
4719            }
4720         }
4721   }
4722
4723    macro_rules! test_vec_1 {
4724        { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
4725            #[simd_test(enable = "altivec")]
4726            fn $name() {
4727                let a = vector_float::from(f32x4::new($($a),+));
4728
4729                let d = vector_float::from(f32x4::new($($d),+));
4730                let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) });
4731                let e = m32x4::new(true, true, true, true);
4732                assert_eq!(e, r);
4733            }
4734        };
4735        { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => {
4736            test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] }
4737        };
4738        { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
4739            #[simd_test(enable = "altivec")]
4740            fn $name() {
4741                let a: s_t_l!($ty) = $ty::new($($a),+).into();
4742
4743                let d = $ty_out::new($($d),+);
4744                let r = $ty_out::from(unsafe { $fn(a) });
4745                assert_eq!(d, r);
4746            }
4747        }
4748    }
4749
4750    #[simd_test(enable = "altivec")]
4751    fn test_vec_ld() {
4752        let pat = [
4753            u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
4754            u8x16::new(
4755                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
4756            ),
4757        ];
4758
4759        for off in 0..16 {
4760            let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) });
4761            assert_eq!(
4762                v,
4763                u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
4764            );
4765        }
4766        for off in 16..32 {
4767            let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) });
4768            assert_eq!(
4769                v,
4770                u8x16::new(
4771                    16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
4772                )
4773            );
4774        }
4775    }
4776
4777    #[simd_test(enable = "altivec")]
4778    fn test_vec_xl() {
4779        let pat = [
4780            u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
4781            u8x16::new(
4782                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
4783            ),
4784        ];
4785
4786        for off in 0..16 {
4787            let val = u8x16::from(unsafe { vec_xl(0, (pat.as_ptr() as *const u8).offset(off)) });
4788            for i in 0..16 {
4789                let v = val.extract_dyn(i);
4790                assert_eq!(off as usize + i, v as usize);
4791            }
4792        }
4793    }
4794
4795    #[simd_test(enable = "altivec")]
4796    fn test_vec_xst() {
4797        let v = vector_unsigned_char::from(u8x16::new(
4798            0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4799        ));
4800
4801        for off in 0..16 {
4802            let mut buf = [0u8; 32];
4803            unsafe {
4804                vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off));
4805            }
4806            for i in 0..16 {
4807                assert_eq!(i as u8, buf[off as usize..][i]);
4808            }
4809        }
4810    }
4811
4812    #[simd_test(enable = "altivec")]
4813    fn test_vec_ldl() {
4814        let pat = [
4815            u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
4816            u8x16::new(
4817                16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
4818            ),
4819        ];
4820
4821        for off in 0..16 {
4822            let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) });
4823            assert_eq!(
4824                v,
4825                u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
4826            );
4827        }
4828        for off in 16..32 {
4829            let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) });
4830            assert_eq!(
4831                v,
4832                u8x16::new(
4833                    16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
4834                )
4835            );
4836        }
4837    }
4838
4839    #[simd_test(enable = "altivec")]
4840    fn test_vec_lde_u8() {
4841        let pat = [u8x16::new(
4842            0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
4843        )];
4844        for off in 0..16 {
4845            let v = u8x16::from(unsafe { vec_lde(off, pat.as_ptr() as *const u8) });
4846            assert_eq!(off as u8, v.extract_dyn(off as _));
4847        }
4848    }
4849
4850    #[simd_test(enable = "altivec")]
4851    fn test_vec_lde_u16() {
4852        let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)];
4853        for off in 0..8 {
4854            let v = u16x8::from(unsafe { vec_lde(off * 2, pat.as_ptr() as *const u16) });
4855            assert_eq!(off as u16, v.extract_dyn(off as _));
4856        }
4857    }
4858
4859    #[simd_test(enable = "altivec")]
4860    fn test_vec_lde_u32() {
4861        let pat = [u32x4::new(0, 1, 2, 3)];
4862        for off in 0..4 {
4863            let v = u32x4::from(unsafe { vec_lde(off * 4, pat.as_ptr() as *const u32) });
4864            assert_eq!(off as u32, v.extract_dyn(off as _));
4865        }
4866    }
4867
4868    test_vec_1! { test_vec_floor, vec_floor, f32x4,
4869        [1.1, 1.9, -0.5, -0.9],
4870        [1.0, 1.0, -1.0, -1.0]
4871    }
4872
4873    test_vec_1! { test_vec_expte, vec_expte, f32x4,
4874        [0.0, 2.0, 2.0, -1.0],
4875        ~[1.0, 4.0, 4.0, 0.5]
4876    }
4877
4878    test_vec_2! { test_vec_cmpgt_i8, vec_cmpgt, i8x16 -> m8x16,
4879        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4880        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4881        [true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false]
4882    }
4883
4884    test_vec_2! { test_vec_cmpgt_u8, vec_cmpgt, u8x16 -> m8x16,
4885        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4886        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4887        [true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
4888    }
4889
4890    test_vec_2! { test_vec_cmpgt_i16, vec_cmpgt, i16x8 -> m16x8,
4891        [1, -1, 0, 0, 0, 0, 0, 0],
4892        [0, 0, -1, 1, 0, 0, 0, 0],
4893        [true, false, true, false, false, false, false, false]
4894    }
4895
4896    test_vec_2! { test_vec_cmpgt_u16, vec_cmpgt, u16x8 -> m16x8,
4897        [1, 255, 0, 0, 0, 0, 0, 0],
4898        [0, 0, 255, 1, 0, 0, 0, 0],
4899        [true, true, false, false, false, false, false, false]
4900    }
4901
4902    test_vec_2! { test_vec_cmpgt_i32, vec_cmpgt, i32x4 -> m32x4,
4903        [1, -1, 0, 0],
4904        [0, -1, 0, 1],
4905        [true, false, false, false]
4906    }
4907
4908    test_vec_2! { test_vec_cmpgt_u32, vec_cmpgt, u32x4 -> m32x4,
4909        [1, 255, 0, 0],
4910        [0, 255,  0, 1],
4911        [true, false, false, false]
4912    }
4913
4914    test_vec_2! { test_vec_cmpge, vec_cmpge, f32x4 -> m32x4,
4915        [0.1, -0.1, 0.0, 0.99],
4916        [0.1, 0.0, 0.1, 1.0],
4917        [true, false, false, false]
4918    }
4919
4920    test_vec_2! { test_vec_cmpeq_i8, vec_cmpeq, i8x16 -> m8x16,
4921        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4922        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4923        [false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true]
4924    }
4925
4926    test_vec_2! { test_vec_cmpeq_u8, vec_cmpeq, u8x16 -> m8x16,
4927        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4928        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4929        [false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true]
4930    }
4931
4932    test_vec_2! { test_vec_cmpeq_i16, vec_cmpeq, i16x8 -> m16x8,
4933        [1, -1, 0, 0, 0, 0, 0, 0],
4934        [0, 0, -1, 1, 0, 0, 0, 0],
4935        [false, false, false, false, true, true, true, true]
4936    }
4937
4938    test_vec_2! { test_vec_cmpeq_u16, vec_cmpeq, u16x8 -> m16x8,
4939        [1, 255, 0, 0, 0, 0, 0, 0],
4940        [0, 0, 255, 1, 0, 0, 0, 0],
4941        [false, false, false, false, true, true, true, true]
4942    }
4943
4944    test_vec_2! { test_vec_cmpeq_i32, vec_cmpeq, i32x4 -> m32x4,
4945        [1, -1, 0, 0],
4946        [0, -1, 0, 1],
4947        [false, true, true, false]
4948    }
4949
4950    test_vec_2! { test_vec_cmpeq_u32, vec_cmpeq, u32x4 -> m32x4,
4951        [1, 255, 0, 0],
4952        [0, 255,  0, 1],
4953        [false, true, true, false]
4954    }
4955
4956    test_vec_2! { test_vec_cmpne_i8, vec_cmpne, i8x16 -> m8x16,
4957        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4958        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4959        [true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false]
4960    }
4961
4962    test_vec_2! { test_vec_cmpne_u8, vec_cmpne, u8x16 -> m8x16,
4963        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4964        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4965        [true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false]
4966    }
4967
4968    test_vec_2! { test_vec_cmpne_i16, vec_cmpne, i16x8 -> m16x8,
4969        [1, -1, 0, 0, 0, 0, 0, 0],
4970        [0, 0, -1, 1, 0, 0, 0, 0],
4971        [true, true, true, true, false, false, false, false]
4972    }
4973
4974    test_vec_2! { test_vec_cmpne_u16, vec_cmpne, u16x8 -> m16x8,
4975        [1, 255, 0, 0, 0, 0, 0, 0],
4976        [0, 0, 255, 1, 0, 0, 0, 0],
4977        [true, true, true, true, false, false, false, false]
4978    }
4979
4980    test_vec_2! { test_vec_cmpne_i32, vec_cmpne, i32x4 -> m32x4,
4981        [1, -1, 0, 0],
4982        [0, -1, 0, 1],
4983        [true, false, false, true]
4984    }
4985
4986    test_vec_2! { test_vec_cmpne_u32, vec_cmpne, u32x4 -> m32x4,
4987        [1, 255, 0, 0],
4988        [0, 255,  0, 1],
4989        [true, false, false, true]
4990    }
4991
4992    test_vec_2! { test_vec_all_eq_i8_false, vec_all_eq, i8x16 -> bool,
4993        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4994        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
4995        false
4996    }
4997
4998    test_vec_2! { test_vec_all_eq_u8_false, vec_all_eq, u8x16 -> bool,
4999        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5000        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5001        false
5002    }
5003
5004    test_vec_2! { test_vec_all_eq_i16_false, vec_all_eq, i16x8 -> bool,
5005        [1, -1, 0, 0, 0, 0, 0, 0],
5006        [0, 0, -1, 1, 0, 0, 0, 0],
5007        false
5008    }
5009
5010    test_vec_2! { test_vec_all_eq_u16_false, vec_all_eq, u16x8 -> bool,
5011        [1, 255, 0, 0, 0, 0, 0, 0],
5012        [0, 0, 255, 1, 0, 0, 0, 0],
5013        false
5014    }
5015
5016    test_vec_2! { test_vec_all_eq_i32_false, vec_all_eq, i32x4 -> bool,
5017        [1, -1, 0, 0],
5018        [0, -1, 0, 1],
5019        false
5020    }
5021
5022    test_vec_2! { test_vec_all_eq_u32_false, vec_all_eq, u32x4 -> bool,
5023        [1, 255, 0, 0],
5024        [0, 255,  0, 1],
5025        false
5026    }
5027
5028    test_vec_2! { test_vec_all_eq_i8_true, vec_all_eq, i8x16 -> bool,
5029        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5030        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5031        true
5032    }
5033
5034    test_vec_2! { test_vec_all_eq_u8_true, vec_all_eq, u8x16 -> bool,
5035        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5036        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5037        true
5038    }
5039
5040    test_vec_2! { test_vec_all_eq_i16_true, vec_all_eq, i16x8 -> bool,
5041        [1, -1, 1, 0, 0, 0, 0, 0],
5042        [1, -1, 1, 0, 0, 0, 0, 0],
5043        true
5044    }
5045
5046    test_vec_2! { test_vec_all_eq_u16_true, vec_all_eq, u16x8 -> bool,
5047        [1, 255, 1, 0, 0, 0, 0, 0],
5048        [1, 255, 1, 0, 0, 0, 0, 0],
5049        true
5050    }
5051
5052    test_vec_2! { test_vec_all_eq_i32_true, vec_all_eq, i32x4 -> bool,
5053        [1, -1, 0, 1],
5054        [1, -1, 0, 1],
5055        true
5056    }
5057
5058    test_vec_2! { test_vec_all_eq_u32_true, vec_all_eq, u32x4 -> bool,
5059        [1, 255, 0, 1],
5060        [1, 255, 0, 1],
5061        true
5062    }
5063
5064    test_vec_2! { test_vec_any_eq_i8_false, vec_any_eq, i8x16 -> bool,
5065        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5066        [0, 0, -1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5067        false
5068    }
5069
5070    test_vec_2! { test_vec_any_eq_u8_false, vec_any_eq, u8x16 -> bool,
5071        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5072        [0, 0, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5073        false
5074    }
5075
5076    test_vec_2! { test_vec_any_eq_i16_false, vec_any_eq, i16x8 -> bool,
5077        [1, -1, 0, 0, 0, 0, 0, 0],
5078        [0, 0, -1, 1, 1, 1, 1, 1],
5079        false
5080    }
5081
5082    test_vec_2! { test_vec_any_eq_u16_false, vec_any_eq, u16x8 -> bool,
5083        [1, 255, 0, 0, 0, 0, 0, 0],
5084        [0, 0, 255, 1, 1, 1, 1, 1],
5085        false
5086    }
5087
5088    test_vec_2! { test_vec_any_eq_i32_false, vec_any_eq, i32x4 -> bool,
5089        [1, -1, 0, 0],
5090        [0, -2, 1, 1],
5091        false
5092    }
5093
5094    test_vec_2! { test_vec_any_eq_u32_false, vec_any_eq, u32x4 -> bool,
5095        [1, 2, 1, 0],
5096        [0, 255,  0, 1],
5097        false
5098    }
5099
5100    test_vec_2! { test_vec_any_eq_i8_true, vec_any_eq, i8x16 -> bool,
5101        [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5102        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5103        true
5104    }
5105
5106    test_vec_2! { test_vec_any_eq_u8_true, vec_any_eq, u8x16 -> bool,
5107        [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5108        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5109        true
5110    }
5111
5112    test_vec_2! { test_vec_any_eq_i16_true, vec_any_eq, i16x8 -> bool,
5113        [0, -1, 1, 0, 0, 0, 0, 0],
5114        [1, -1, 1, 0, 0, 0, 0, 0],
5115        true
5116    }
5117
5118    test_vec_2! { test_vec_any_eq_u16_true, vec_any_eq, u16x8 -> bool,
5119        [0, 255, 1, 0, 0, 0, 0, 0],
5120        [1, 255, 1, 0, 0, 0, 0, 0],
5121        true
5122    }
5123
5124    test_vec_2! { test_vec_any_eq_i32_true, vec_any_eq, i32x4 -> bool,
5125        [0, -1, 0, 1],
5126        [1, -1, 0, 1],
5127        true
5128    }
5129
5130    test_vec_2! { test_vec_any_eq_u32_true, vec_any_eq, u32x4 -> bool,
5131        [0, 255, 0, 1],
5132        [1, 255, 0, 1],
5133        true
5134    }
5135
5136    test_vec_2! { test_vec_all_ge_i8_false, vec_all_ge, i8x16 -> bool,
5137        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5138        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5139        false
5140    }
5141
5142    test_vec_2! { test_vec_all_ge_u8_false, vec_all_ge, u8x16 -> bool,
5143        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5144        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5145        false
5146    }
5147
5148    test_vec_2! { test_vec_all_ge_i16_false, vec_all_ge, i16x8 -> bool,
5149        [1, -1, 0, 0, 0, 0, 0, 0],
5150        [0, 0, -1, 1, 0, 0, 0, 0],
5151        false
5152    }
5153
5154    test_vec_2! { test_vec_all_ge_u16_false, vec_all_ge, u16x8 -> bool,
5155        [1, 255, 0, 0, 0, 0, 0, 0],
5156        [0, 0, 255, 1, 0, 0, 0, 0],
5157        false
5158    }
5159
5160    test_vec_2! { test_vec_all_ge_i32_false, vec_all_ge, i32x4 -> bool,
5161        [1, -1, 0, 0],
5162        [0, -1, 0, 1],
5163        false
5164    }
5165
5166    test_vec_2! { test_vec_all_ge_u32_false, vec_all_ge, u32x4 -> bool,
5167        [1, 255, 0, 0],
5168        [0, 255,  1, 1],
5169        false
5170    }
5171
5172    test_vec_2! { test_vec_all_ge_i8_true, vec_all_ge, i8x16 -> bool,
5173        [0, 0, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5174        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5175        true
5176    }
5177
5178    test_vec_2! { test_vec_all_ge_u8_true, vec_all_ge, u8x16 -> bool,
5179        [1, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5180        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5181        true
5182    }
5183
5184    test_vec_2! { test_vec_all_ge_i16_true, vec_all_ge, i16x8 -> bool,
5185        [1, -1, 42, 0, 0, 0, 0, 0],
5186        [1, -5, 2, 0, 0, 0, 0, 0],
5187        true
5188    }
5189
5190    test_vec_2! { test_vec_all_ge_u16_true, vec_all_ge, u16x8 -> bool,
5191        [42, 255, 1, 0, 0, 0, 0, 0],
5192        [2, 255, 1, 0, 0, 0, 0, 0],
5193        true
5194    }
5195
5196    test_vec_2! { test_vec_all_ge_i32_true, vec_all_ge, i32x4 -> bool,
5197        [1, -1, 0, 1],
5198        [0, -1, 0, 1],
5199        true
5200    }
5201
5202    test_vec_2! { test_vec_all_ge_u32_true, vec_all_ge, u32x4 -> bool,
5203        [1, 255, 0, 1],
5204        [1, 254, 0, 0],
5205        true
5206    }
5207
5208    test_vec_2! { test_vec_any_ge_i8_false, vec_any_ge, i8x16 -> bool,
5209        [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5210        [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5211        false
5212    }
5213
5214    test_vec_2! { test_vec_any_ge_u8_false, vec_any_ge, u8x16 -> bool,
5215        [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5216        [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5217        false
5218    }
5219
5220    test_vec_2! { test_vec_any_ge_i16_false, vec_any_ge, i16x8 -> bool,
5221        [1, -1, -2, 0, 0, 0, 0, 0],
5222        [2, 0, -1, 1, 1, 1, 1, 1],
5223        false
5224    }
5225
5226    test_vec_2! { test_vec_any_ge_u16_false, vec_any_ge, u16x8 -> bool,
5227        [1, 2, 0, 0, 0, 0, 0, 0],
5228        [2, 42, 255, 1, 1, 1, 1, 1],
5229        false
5230    }
5231
5232    test_vec_2! { test_vec_any_ge_i32_false, vec_any_ge, i32x4 -> bool,
5233        [1, -1, 0, 0],
5234        [2, 0, 1, 1],
5235        false
5236    }
5237
5238    test_vec_2! { test_vec_any_ge_u32_false, vec_any_ge, u32x4 -> bool,
5239        [1, 2, 1, 0],
5240        [4, 255,  4, 1],
5241        false
5242    }
5243
5244    test_vec_2! { test_vec_any_ge_i8_true, vec_any_ge, i8x16 -> bool,
5245        [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5246        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5247        true
5248    }
5249
5250    test_vec_2! { test_vec_any_ge_u8_true, vec_any_ge, u8x16 -> bool,
5251        [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5252        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5253        true
5254    }
5255
5256    test_vec_2! { test_vec_any_ge_i16_true, vec_any_ge, i16x8 -> bool,
5257        [0, -1, 1, 0, 0, 0, 0, 0],
5258        [1, -1, 1, 0, 0, 0, 0, 0],
5259        true
5260    }
5261
5262    test_vec_2! { test_vec_any_ge_u16_true, vec_any_ge, u16x8 -> bool,
5263        [0, 255, 1, 0, 0, 0, 0, 0],
5264        [1, 255, 1, 0, 0, 0, 0, 0],
5265        true
5266    }
5267
5268    test_vec_2! { test_vec_any_ge_i32_true, vec_any_ge, i32x4 -> bool,
5269        [0, -1, 0, 1],
5270        [1, -1, 0, 1],
5271        true
5272    }
5273
5274    test_vec_2! { test_vec_any_ge_u32_true, vec_any_ge, u32x4 -> bool,
5275        [0, 255, 0, 1],
5276        [1, 255, 0, 1],
5277        true
5278    }
5279
5280    test_vec_2! { test_vec_all_gt_i8_false, vec_all_gt, i8x16 -> bool,
5281        [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5282        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5283        false
5284    }
5285
5286    test_vec_2! { test_vec_all_gt_u8_false, vec_all_gt, u8x16 -> bool,
5287        [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5288        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5289        false
5290    }
5291
5292    test_vec_2! { test_vec_all_gt_i16_false, vec_all_gt, i16x8 -> bool,
5293        [1, 0, 0, 0, 0, 0, 0, 0],
5294        [0, 0, -1, 1, 0, 0, 0, 0],
5295        false
5296    }
5297
5298    test_vec_2! { test_vec_all_gt_u16_false, vec_all_gt, u16x8 -> bool,
5299        [1, 0, 0, 0, 0, 0, 0, 0],
5300        [0, 0, 255, 1, 0, 0, 0, 0],
5301        false
5302    }
5303
5304    test_vec_2! { test_vec_all_gt_i32_false, vec_all_gt, i32x4 -> bool,
5305        [1, -1, 0, 0],
5306        [0, -1, 0, 1],
5307        false
5308    }
5309
5310    test_vec_2! { test_vec_all_gt_u32_false, vec_all_gt, u32x4 -> bool,
5311        [1, 255, 0, 0],
5312        [0, 255,  1, 1],
5313        false
5314    }
5315
5316    test_vec_2! { test_vec_all_gt_i8_true, vec_all_gt, i8x16 -> bool,
5317        [2, 1, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5318        [0, 0, -2, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1],
5319        true
5320    }
5321
5322    test_vec_2! { test_vec_all_gt_u8_true, vec_all_gt, u8x16 -> bool,
5323        [1, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5324        [0, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5325        true
5326    }
5327
5328    test_vec_2! { test_vec_all_gt_i16_true, vec_all_gt, i16x8 -> bool,
5329        [1, -1, 42, 1, 1, 1, 1, 1],
5330        [0, -5, 2, 0, 0, 0, 0, 0],
5331        true
5332    }
5333
5334    test_vec_2! { test_vec_all_gt_u16_true, vec_all_gt, u16x8 -> bool,
5335        [42, 255, 1, 1, 1, 1, 1, 1],
5336        [2, 254, 0, 0, 0, 0, 0, 0],
5337        true
5338    }
5339
5340    test_vec_2! { test_vec_all_gt_i32_true, vec_all_gt, i32x4 -> bool,
5341        [1, -1, 1, 1],
5342        [0, -2, 0, 0],
5343        true
5344    }
5345
5346    test_vec_2! { test_vec_all_gt_u32_true, vec_all_gt, u32x4 -> bool,
5347        [1, 255, 1, 1],
5348        [0, 254, 0, 0],
5349        true
5350    }
5351
5352    test_vec_2! { test_vec_any_gt_i8_false, vec_any_gt, i8x16 -> bool,
5353        [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5354        [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5355        false
5356    }
5357
5358    test_vec_2! { test_vec_any_gt_u8_false, vec_any_gt, u8x16 -> bool,
5359        [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5360        [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5361        false
5362    }
5363
5364    test_vec_2! { test_vec_any_gt_i16_false, vec_any_gt, i16x8 -> bool,
5365        [1, -1, -2, 0, 0, 0, 0, 0],
5366        [2, 0, -1, 1, 1, 1, 1, 1],
5367        false
5368    }
5369
5370    test_vec_2! { test_vec_any_gt_u16_false, vec_any_gt, u16x8 -> bool,
5371        [1, 2, 0, 0, 0, 0, 0, 0],
5372        [2, 42, 255, 1, 1, 1, 1, 1],
5373        false
5374    }
5375
5376    test_vec_2! { test_vec_any_gt_i32_false, vec_any_gt, i32x4 -> bool,
5377        [1, -1, 0, 0],
5378        [2, 0, 1, 1],
5379        false
5380    }
5381
5382    test_vec_2! { test_vec_any_gt_u32_false, vec_any_gt, u32x4 -> bool,
5383        [1, 2, 1, 0],
5384        [4, 255,  4, 1],
5385        false
5386    }
5387
5388    test_vec_2! { test_vec_any_gt_i8_true, vec_any_gt, i8x16 -> bool,
5389        [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5390        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5391        true
5392    }
5393
5394    test_vec_2! { test_vec_any_gt_u8_true, vec_any_gt, u8x16 -> bool,
5395        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5396        [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5397        true
5398    }
5399
5400    test_vec_2! { test_vec_any_gt_i16_true, vec_any_gt, i16x8 -> bool,
5401        [1, -1, 1, 0, 0, 0, 0, 0],
5402        [0, -1, 1, 0, 0, 0, 0, 0],
5403        true
5404    }
5405
5406    test_vec_2! { test_vec_any_gt_u16_true, vec_any_gt, u16x8 -> bool,
5407        [1, 255, 1, 0, 0, 0, 0, 0],
5408        [0, 255, 1, 0, 0, 0, 0, 0],
5409        true
5410    }
5411
5412    test_vec_2! { test_vec_any_gt_i32_true, vec_any_gt, i32x4 -> bool,
5413        [1, -1, 0, 1],
5414        [0, -1, 0, 1],
5415        true
5416    }
5417
5418    test_vec_2! { test_vec_any_gt_u32_true, vec_any_gt, u32x4 -> bool,
5419        [1, 255, 0, 1],
5420        [0, 255, 0, 1],
5421        true
5422    }
5423
5424    test_vec_2! { test_vec_all_in_true, vec_all_in, f32x4 -> bool,
5425        [0.0, -0.1, 0.0, 0.0],
5426        [0.1, 0.2, 0.0, 0.0],
5427        true
5428    }
5429
5430    test_vec_2! { test_vec_all_in_false, vec_all_in, f32x4 -> bool,
5431        [0.5, 0.4, -0.5, 0.8],
5432        [0.1, 0.4, -0.5, 0.8],
5433        false
5434    }
5435
5436    test_vec_2! { test_vec_all_le_i8_false, vec_all_le, i8x16 -> bool,
5437        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5438        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5439        false
5440    }
5441
5442    test_vec_2! { test_vec_all_le_u8_false, vec_all_le, u8x16 -> bool,
5443        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5444        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5445        false
5446    }
5447
5448    test_vec_2! { test_vec_all_le_i16_false, vec_all_le, i16x8 -> bool,
5449        [0, 0, -1, 1, 0, 0, 0, 0],
5450        [1, -1, 0, 0, 0, 0, 0, 0],
5451        false
5452    }
5453
5454    test_vec_2! { test_vec_all_le_u16_false, vec_all_le, u16x8 -> bool,
5455        [0, 0, 255, 1, 0, 0, 0, 0],
5456        [1, 255, 0, 0, 0, 0, 0, 0],
5457        false
5458    }
5459
5460    test_vec_2! { test_vec_all_le_i32_false, vec_all_le, i32x4 -> bool,
5461        [0, -1, 0, 1],
5462        [1, -1, 0, 0],
5463        false
5464    }
5465
5466    test_vec_2! { test_vec_all_le_u32_false, vec_all_le, u32x4 -> bool,
5467        [0, 255,  1, 1],
5468        [1, 255, 0, 0],
5469        false
5470    }
5471
5472    test_vec_2! { test_vec_all_le_i8_true, vec_all_le, i8x16 -> bool,
5473        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5474        [0, 0, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5475        true
5476    }
5477
5478    test_vec_2! { test_vec_all_le_u8_true, vec_all_le, u8x16 -> bool,
5479        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5480        [1, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5481        true
5482    }
5483
5484    test_vec_2! { test_vec_all_le_i16_true, vec_all_le, i16x8 -> bool,
5485        [1, -5, 2, 0, 0, 0, 0, 0],
5486        [1, -1, 42, 0, 0, 0, 0, 0],
5487        true
5488    }
5489
5490    test_vec_2! { test_vec_all_le_u16_true, vec_all_le, u16x8 -> bool,
5491        [2, 255, 1, 0, 0, 0, 0, 0],
5492        [42, 255, 1, 0, 0, 0, 0, 0],
5493        true
5494    }
5495
5496    test_vec_2! { test_vec_all_le_i32_true, vec_all_le, i32x4 -> bool,
5497        [0, -1, 0, 1],
5498        [1, -1, 0, 1],
5499        true
5500    }
5501
5502    test_vec_2! { test_vec_all_le_u32_true, vec_all_le, u32x4 -> bool,
5503        [1, 254, 0, 0],
5504        [1, 255, 0, 1],
5505        true
5506    }
5507
5508    test_vec_2! { test_vec_any_le_i8_false, vec_any_le, i8x16 -> bool,
5509        [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5510        [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5511        false
5512    }
5513
5514    test_vec_2! { test_vec_any_le_u8_false, vec_any_le, u8x16 -> bool,
5515        [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5516        [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5517        false
5518    }
5519
5520    test_vec_2! { test_vec_any_le_i16_false, vec_any_le, i16x8 -> bool,
5521        [2, 0, -1, 1, 1, 1, 1, 1],
5522        [1, -1, -2, 0, 0, 0, 0, 0],
5523        false
5524    }
5525
5526    test_vec_2! { test_vec_any_le_u16_false, vec_any_le, u16x8 -> bool,
5527        [2, 42, 255, 1, 1, 1, 1, 1],
5528        [1, 2, 0, 0, 0, 0, 0, 0],
5529        false
5530    }
5531
5532    test_vec_2! { test_vec_any_le_i32_false, vec_any_le, i32x4 -> bool,
5533        [2, 0, 1, 1],
5534        [1, -1, 0, 0],
5535        false
5536    }
5537
5538    test_vec_2! { test_vec_any_le_u32_false, vec_any_le, u32x4 -> bool,
5539        [4, 255,  4, 1],
5540        [1, 2, 1, 0],
5541        false
5542    }
5543
5544    test_vec_2! { test_vec_any_le_i8_true, vec_any_le, i8x16 -> bool,
5545        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5546        [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5547        true
5548    }
5549
5550    test_vec_2! { test_vec_any_le_u8_true, vec_any_le, u8x16 -> bool,
5551        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5552        [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5553        true
5554    }
5555
5556    test_vec_2! { test_vec_any_le_i16_true, vec_any_le, i16x8 -> bool,
5557        [1, -1, 1, 0, 0, 0, 0, 0],
5558        [0, -1, 1, 0, 0, 0, 0, 0],
5559        true
5560    }
5561
5562    test_vec_2! { test_vec_any_le_u16_true, vec_any_le, u16x8 -> bool,
5563        [1, 255, 1, 0, 0, 0, 0, 0],
5564        [0, 255, 1, 0, 0, 0, 0, 0],
5565        true
5566    }
5567
5568    test_vec_2! { test_vec_any_le_i32_true, vec_any_le, i32x4 -> bool,
5569        [1, -1, 0, 1],
5570        [0, -1, 0, 1],
5571        true
5572    }
5573
5574    test_vec_2! { test_vec_any_le_u32_true, vec_any_le, u32x4 -> bool,
5575        [1, 255, 0, 1],
5576        [0, 255, 0, 1],
5577        true
5578    }
5579
5580    test_vec_2! { test_vec_all_lt_i8_false, vec_all_lt, i8x16 -> bool,
5581        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5582        [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5583        false
5584    }
5585
5586    test_vec_2! { test_vec_all_lt_u8_false, vec_all_lt, u8x16 -> bool,
5587        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5588        [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5589        false
5590    }
5591
5592    test_vec_2! { test_vec_all_lt_i16_false, vec_all_lt, i16x8 -> bool,
5593        [0, 0, -1, 1, 0, 0, 0, 0],
5594        [1, 0, 0, 0, 0, 0, 0, 0],
5595        false
5596    }
5597
5598    test_vec_2! { test_vec_all_lt_u16_false, vec_all_lt, u16x8 -> bool,
5599        [0, 0, 255, 1, 0, 0, 0, 0],
5600        [1, 0, 0, 0, 0, 0, 0, 0],
5601        false
5602    }
5603
5604    test_vec_2! { test_vec_all_lt_i32_false, vec_all_lt, i32x4 -> bool,
5605        [0, -1, 0, 1],
5606        [1, -1, 0, 0],
5607        false
5608    }
5609
5610    test_vec_2! { test_vec_all_lt_u32_false, vec_all_lt, u32x4 -> bool,
5611        [0, 255,  1, 1],
5612        [1, 255, 0, 0],
5613        false
5614    }
5615
5616    test_vec_2! { test_vec_all_lt_i8_true, vec_all_lt, i8x16 -> bool,
5617        [0, 0, -2, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1],
5618        [2, 1, -1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0],
5619        true
5620    }
5621
5622    test_vec_2! { test_vec_all_lt_u8_true, vec_all_lt, u8x16 -> bool,
5623        [0, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5624        [1, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5625        true
5626    }
5627
5628    test_vec_2! { test_vec_all_lt_i16_true, vec_all_lt, i16x8 -> bool,
5629        [0, -5, 2, 0, 0, 0, 0, 0],
5630        [1, -1, 42, 1, 1, 1, 1, 1],
5631        true
5632    }
5633
5634    test_vec_2! { test_vec_all_lt_u16_true, vec_all_lt, u16x8 -> bool,
5635        [2, 254, 0, 0, 0, 0, 0, 0],
5636        [42, 255, 1, 1, 1, 1, 1, 1],
5637        true
5638    }
5639
5640    test_vec_2! { test_vec_all_lt_i32_true, vec_all_lt, i32x4 -> bool,
5641        [0, -2, 0, 0],
5642        [1, -1, 1, 1],
5643        true
5644    }
5645
5646    test_vec_2! { test_vec_all_lt_u32_true, vec_all_lt, u32x4 -> bool,
5647        [0, 254, 0, 0],
5648        [1, 255, 1, 1],
5649        true
5650    }
5651
5652    test_vec_2! { test_vec_any_lt_i8_false, vec_any_lt, i8x16 -> bool,
5653        [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5654        [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5655        false
5656    }
5657
5658    test_vec_2! { test_vec_any_lt_u8_false, vec_any_lt, u8x16 -> bool,
5659        [42, 255, 255, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5660        [1, 254, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5661        false
5662    }
5663
5664    test_vec_2! { test_vec_any_lt_i16_false, vec_any_lt, i16x8 -> bool,
5665        [2, 0, -1, 1, 1, 1, 1, 1],
5666        [1, -1, -2, 0, 0, 0, 0, 0],
5667        false
5668    }
5669
5670    test_vec_2! { test_vec_any_lt_u16_false, vec_any_lt, u16x8 -> bool,
5671        [2, 42, 255, 1, 1, 1, 1, 1],
5672        [1, 2, 0, 0, 0, 0, 0, 0],
5673        false
5674    }
5675
5676    test_vec_2! { test_vec_any_lt_i32_false, vec_any_lt, i32x4 -> bool,
5677        [2, 0, 1, 1],
5678        [1, -1, 0, 0],
5679        false
5680    }
5681
5682    test_vec_2! { test_vec_any_lt_u32_false, vec_any_lt, u32x4 -> bool,
5683        [4, 255,  4, 1],
5684        [1, 2, 1, 0],
5685        false
5686    }
5687
5688    test_vec_2! { test_vec_any_lt_i8_true, vec_any_lt, i8x16 -> bool,
5689        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5690        [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5691        true
5692    }
5693
5694    test_vec_2! { test_vec_any_lt_u8_true, vec_any_lt, u8x16 -> bool,
5695        [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5696        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5697        true
5698    }
5699
5700    test_vec_2! { test_vec_any_lt_i16_true, vec_any_lt, i16x8 -> bool,
5701        [0, -1, 1, 0, 0, 0, 0, 0],
5702        [1, -1, 1, 0, 0, 0, 0, 0],
5703        true
5704    }
5705
5706    test_vec_2! { test_vec_any_lt_u16_true, vec_any_lt, u16x8 -> bool,
5707        [0, 255, 1, 0, 0, 0, 0, 0],
5708        [1, 255, 1, 0, 0, 0, 0, 0],
5709        true
5710    }
5711
5712    test_vec_2! { test_vec_any_lt_i32_true, vec_any_lt, i32x4 -> bool,
5713        [0, -1, 0, 1],
5714        [1, -1, 0, 1],
5715        true
5716    }
5717
5718    test_vec_2! { test_vec_any_lt_u32_true, vec_any_lt, u32x4 -> bool,
5719        [0, 255, 0, 1],
5720        [1, 255, 0, 1],
5721        true
5722    }
5723
5724    test_vec_2! { test_vec_all_ne_i8_false, vec_all_ne, i8x16 -> bool,
5725        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5726        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5727        false
5728    }
5729
5730    test_vec_2! { test_vec_all_ne_u8_false, vec_all_ne, u8x16 -> bool,
5731        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5732        [0, 0, 255, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5733        false
5734    }
5735
5736    test_vec_2! { test_vec_all_ne_i16_false, vec_all_ne, i16x8 -> bool,
5737        [1, -1, 0, 0, 0, 0, 0, 0],
5738        [0, -1, 1, 0, 0, 0, 0, 0],
5739        false
5740    }
5741
5742    test_vec_2! { test_vec_all_ne_u16_false, vec_all_ne, u16x8 -> bool,
5743        [1, 255, 0, 0, 0, 0, 0, 0],
5744        [0, 255, 0, 1, 0, 0, 0, 0],
5745        false
5746    }
5747
5748    test_vec_2! { test_vec_all_ne_i32_false, vec_all_ne, i32x4 -> bool,
5749        [1, -1, 0, 0],
5750        [0, -1, 0, 1],
5751        false
5752    }
5753
5754    test_vec_2! { test_vec_all_ne_u32_false, vec_all_ne, u32x4 -> bool,
5755        [1, 255, 0, 0],
5756        [0, 255,  0, 1],
5757        false
5758    }
5759
5760    test_vec_2! { test_vec_all_ne_i8_true, vec_all_ne, i8x16 -> bool,
5761        [0, -1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5762        [1, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5763        true
5764    }
5765
5766    test_vec_2! { test_vec_all_ne_u8_true, vec_all_ne, u8x16 -> bool,
5767        [0, 254, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
5768        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5769        true
5770    }
5771
5772    test_vec_2! { test_vec_all_ne_i16_true, vec_all_ne, i16x8 -> bool,
5773        [2, -2, 0, 1, 1, 1, 1, 1],
5774        [1, -1, 1, 0, 0, 0, 0, 0],
5775        true
5776    }
5777
5778    test_vec_2! { test_vec_all_ne_u16_true, vec_all_ne, u16x8 -> bool,
5779        [0, 254, 1, 1, 0, 0, 1, 0],
5780        [1, 255, 0, 0, 1, 1, 0, 1],
5781        true
5782    }
5783
5784    test_vec_2! { test_vec_all_ne_i32_true, vec_all_ne, i32x4 -> bool,
5785        [0, -2, 0, 0],
5786        [1, -1, 1, 1],
5787        true
5788    }
5789
5790    test_vec_2! { test_vec_all_ne_u32_true, vec_all_ne, u32x4 -> bool,
5791        [1, 255, 0, 0],
5792        [0, 254, 1, 1],
5793        true
5794    }
5795
5796    test_vec_2! { test_vec_any_ne_i8_false, vec_any_ne, i8x16 -> bool,
5797        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5798        [1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5799        false
5800    }
5801
5802    test_vec_2! { test_vec_any_ne_u8_false, vec_any_ne, u8x16 -> bool,
5803        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5804        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5805        false
5806    }
5807
5808    test_vec_2! { test_vec_any_ne_i16_false, vec_any_ne, i16x8 -> bool,
5809        [1, -1, 0, 0, 0, 0, 0, 0],
5810        [1, -1, 0, 0, 0, 0, 0, 0],
5811        false
5812    }
5813
5814    test_vec_2! { test_vec_any_ne_u16_false, vec_any_ne, u16x8 -> bool,
5815        [1, 255, 1, 1, 1, 1, 1, 0],
5816        [1, 255, 1, 1, 1, 1, 1, 0],
5817        false
5818    }
5819
5820    test_vec_2! { test_vec_any_ne_i32_false, vec_any_ne, i32x4 -> bool,
5821        [0, -1, 1, 1],
5822        [0, -1, 1, 1],
5823        false
5824    }
5825
5826    test_vec_2! { test_vec_any_ne_u32_false, vec_any_ne, u32x4 -> bool,
5827        [1, 2, 1, 255],
5828        [1, 2, 1, 255],
5829        false
5830    }
5831
5832    test_vec_2! { test_vec_any_ne_i8_true, vec_any_ne, i8x16 -> bool,
5833        [1, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5834        [0, 0, -1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5835        true
5836    }
5837
5838    test_vec_2! { test_vec_any_ne_u8_true, vec_any_ne, u8x16 -> bool,
5839        [0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5840        [1, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5841        true
5842    }
5843
5844    test_vec_2! { test_vec_any_ne_i16_true, vec_any_ne, i16x8 -> bool,
5845        [0, -1, 1, 0, 0, 0, 0, 0],
5846        [1, -1, 1, 0, 0, 0, 0, 0],
5847        true
5848    }
5849
5850    test_vec_2! { test_vec_any_ne_u16_true, vec_any_ne, u16x8 -> bool,
5851        [0, 255, 1, 0, 0, 0, 0, 0],
5852        [1, 255, 1, 0, 0, 0, 0, 0],
5853        true
5854    }
5855
5856    test_vec_2! { test_vec_any_ne_i32_true, vec_any_ne, i32x4 -> bool,
5857        [0, -1, 0, 1],
5858        [1, -1, 0, 1],
5859        true
5860    }
5861
5862    test_vec_2! { test_vec_any_ne_u32_true, vec_any_ne, u32x4 -> bool,
5863        [0, 255, 0, 1],
5864        [1, 255, 0, 1],
5865        true
5866    }
5867
5868    #[simd_test(enable = "altivec")]
5869    fn test_vec_cmpb() {
5870        let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9));
5871        let b = vector_float::from(f32x4::new(-0.1, 0.5, -0.6, 0.9));
5872        let d = i32x4::new(
5873            -0b10000000000000000000000000000000,
5874            0,
5875            -0b10000000000000000000000000000000,
5876            0,
5877        );
5878
5879        assert_eq!(d, i32x4::from(unsafe { vec_cmpb(a, b) }));
5880    }
5881
5882    #[simd_test(enable = "altivec")]
5883    fn test_vec_ceil() {
5884        let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9));
5885        let d = f32x4::new(1.0, 1.0, 1.0, 1.0);
5886
5887        assert_eq!(d, f32x4::from(unsafe { vec_ceil(a) }));
5888    }
5889
5890    test_vec_2! { test_vec_andc, vec_andc, i32x4,
5891    [0b11001100, 0b11001100, 0b11001100, 0b11001100],
5892    [0b00110011, 0b11110011, 0b00001100, 0b10000000],
5893    [0b11001100, 0b00001100, 0b11000000, 0b01001100] }
5894
5895    test_vec_2! { test_vec_and, vec_and, i32x4,
5896    [0b11001100, 0b11001100, 0b11001100, 0b11001100],
5897    [0b00110011, 0b11110011, 0b00001100, 0b00000000],
5898    [0b00000000, 0b11000000, 0b00001100, 0b00000000] }
5899
5900    macro_rules! test_vec_avg {
5901        { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
5902            test_vec_2! {$name, vec_avg, $ty, [$($a),+], [$($b),+], [$($d),+] }
5903        }
5904    }
5905
5906    test_vec_avg! { test_vec_avg_i32x4, i32x4,
5907    [i32::MIN, i32::MAX, 1, -1],
5908    [-1, 1, 1, -1],
5909    [-1073741824, 1073741824, 1, -1] }
5910
5911    test_vec_avg! { test_vec_avg_u32x4, u32x4,
5912    [u32::MAX, 0, 1, 2],
5913    [2, 1, 0, 0],
5914    [2147483649, 1, 1, 1] }
5915
5916    test_vec_avg! { test_vec_avg_i16x8, i16x8,
5917    [i16::MIN, i16::MAX, 1, -1, 0, 0, 0, 0],
5918    [-1, 1, 1, -1, 0, 0, 0, 0],
5919    [-16384, 16384, 1, -1, 0, 0, 0, 0] }
5920
5921    test_vec_avg! { test_vec_avg_u16x8, u16x8,
5922    [u16::MAX, 0, 1, 2, 0, 0, 0, 0],
5923    [2, 1, 0, 0, 0, 0, 0, 0],
5924    [32769, 1, 1, 1, 0, 0, 0, 0] }
5925
5926    test_vec_avg! { test_vec_avg_i8x16, i8x16,
5927    [i8::MIN, i8::MAX, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5928    [-1, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5929    [-64, 64, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5930
5931    test_vec_avg! { test_vec_avg_u8x16, u8x16,
5932    [u8::MAX, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5933    [2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5934    [129, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5935
5936    macro_rules! test_vec_adds {
5937        { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
5938            test_vec_2! {$name, vec_adds, $ty, [$($a),+], [$($b),+], [$($d),+] }
5939        }
5940    }
5941
5942    test_vec_adds! { test_vec_adds_i32x4, i32x4,
5943    [i32::MIN, i32::MAX, 1, -1],
5944    [-1, 1, 1, -1],
5945    [i32::MIN, i32::MAX, 2, -2] }
5946
5947    test_vec_adds! { test_vec_adds_u32x4, u32x4,
5948    [u32::MAX, 0, 1, 2],
5949    [2, 1, 0, 0],
5950    [u32::MAX, 1, 1, 2] }
5951
5952    test_vec_adds! { test_vec_adds_i16x8, i16x8,
5953    [i16::MIN, i16::MAX, 1, -1, 0, 0, 0, 0],
5954    [-1, 1, 1, -1, 0, 0, 0, 0],
5955    [i16::MIN, i16::MAX, 2, -2, 0, 0, 0, 0] }
5956
5957    test_vec_adds! { test_vec_adds_u16x8, u16x8,
5958    [u16::MAX, 0, 1, 2, 0, 0, 0, 0],
5959    [2, 1, 0, 0, 0, 0, 0, 0],
5960    [u16::MAX, 1, 1, 2, 0, 0, 0, 0] }
5961
5962    test_vec_adds! { test_vec_adds_i8x16, i8x16,
5963    [i8::MIN, i8::MAX, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5964    [-1, 1, 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5965    [i8::MIN, i8::MAX, 2, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5966
5967    test_vec_adds! { test_vec_adds_u8x16, u8x16,
5968    [u8::MAX, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5969    [2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
5970    [u8::MAX, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
5971
5972    test_vec_2! { test_vec_addc, vec_addc, u32x4, [u32::MAX, 0, 0, 0], [1, 1, 1, 1], [1, 0, 0, 0] }
5973
5974    macro_rules! test_vec_abs {
5975        { $name: ident, $ty: ident, $a: expr, $d: expr } => {
5976            #[simd_test(enable = "altivec")]
5977            fn $name() {
5978                let a = unsafe { vec_splats($a) };
5979                let a: s_t_l!($ty) = unsafe { vec_abs(a) };
5980                let d = $ty::splat($d);
5981                assert_eq!(d, $ty::from(a));
5982            }
5983        }
5984    }
5985
5986    test_vec_abs! { test_vec_abs_i8, i8x16, -42i8, 42i8 }
5987    test_vec_abs! { test_vec_abs_i16, i16x8, -42i16, 42i16 }
5988    test_vec_abs! { test_vec_abs_i32, i32x4, -42i32, 42i32 }
5989    test_vec_abs! { test_vec_abs_f32, f32x4, -42f32, 42f32 }
5990
5991    macro_rules! test_vec_abss {
5992        { $name: ident, $ty: ident, $a: expr, $d: expr } => {
5993            #[simd_test(enable = "altivec")]
5994            fn $name() {
5995                let a = unsafe { vec_splats($a) };
5996                let a: s_t_l!($ty) = unsafe { vec_abss(a) };
5997                let d = $ty::splat($d);
5998                assert_eq!(d, $ty::from(a));
5999            }
6000        }
6001    }
6002
6003    test_vec_abss! { test_vec_abss_i8, i8x16, -127i8, 127i8 }
6004    test_vec_abss! { test_vec_abss_i16, i16x8, -42i16, 42i16 }
6005    test_vec_abss! { test_vec_abss_i32, i32x4, -42i32, 42i32 }
6006
6007    macro_rules! test_vec_splats {
6008        { $name: ident, $ty: ident, $a: expr } => {
6009            #[simd_test(enable = "altivec")]
6010            fn $name() {
6011                let a: s_t_l!($ty) = unsafe { vec_splats($a) };
6012                let d = $ty::splat($a);
6013                assert_eq!(d, $ty::from(a));
6014            }
6015        }
6016    }
6017
6018    test_vec_splats! { test_vec_splats_u8, u8x16, 42u8 }
6019    test_vec_splats! { test_vec_splats_u16, u16x8, 42u16 }
6020    test_vec_splats! { test_vec_splats_u32, u32x4, 42u32 }
6021    test_vec_splats! { test_vec_splats_i8, i8x16, 42i8 }
6022    test_vec_splats! { test_vec_splats_i16, i16x8, 42i16 }
6023    test_vec_splats! { test_vec_splats_i32, i32x4, 42i32 }
6024    test_vec_splats! { test_vec_splats_f32, f32x4, 42f32 }
6025
6026    macro_rules! test_vec_splat {
6027        { $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => {
6028            #[simd_test(enable = "altivec")]
6029            fn $name() {
6030                let a = unsafe { $fun::<$a>() };
6031                let d = $ty::splat($b);
6032                assert_eq!(d, $ty::from(a));
6033            }
6034        }
6035    }
6036
6037    test_vec_splat! { test_vec_splat_u8, vec_splat_u8, u8x16, -1, u8::MAX }
6038    test_vec_splat! { test_vec_splat_u16, vec_splat_u16, u16x8, -1, u16::MAX }
6039    test_vec_splat! { test_vec_splat_u32, vec_splat_u32, u32x4, -1, u32::MAX }
6040    test_vec_splat! { test_vec_splat_s8, vec_splat_s8, i8x16, -1, -1 }
6041    test_vec_splat! { test_vec_splat_s16, vec_splat_s16, i16x8, -1, -1 }
6042    test_vec_splat! { test_vec_splat_s32, vec_splat_s32, i32x4, -1, -1 }
6043
6044    macro_rules! test_vec_sub {
6045        { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6046            test_vec_2! {$name, vec_sub, $ty, [$($a),+], [$($b),+], [$($d),+] }
6047        }
6048    }
6049
6050    test_vec_sub! { test_vec_sub_f32x4, f32x4,
6051    [-1.0, 0.0, 1.0, 2.0],
6052    [2.0, 1.0, -1.0, -2.0],
6053    [-3.0, -1.0, 2.0, 4.0] }
6054
6055    test_vec_sub! { test_vec_sub_i32x4, i32x4,
6056    [-1, 0, 1, 2],
6057    [2, 1, -1, -2],
6058    [-3, -1, 2, 4] }
6059
6060    test_vec_sub! { test_vec_sub_u32x4, u32x4,
6061    [0, 0, 1, 2],
6062    [2, 1, 0, 0],
6063    [4294967294, 4294967295, 1, 2] }
6064
6065    test_vec_sub! { test_vec_sub_i16x8, i16x8,
6066    [-1, 0, 1, 2, -1, 0, 1, 2],
6067    [2, 1, -1, -2, 2, 1, -1, -2],
6068    [-3, -1, 2, 4, -3, -1, 2, 4] }
6069
6070    test_vec_sub! { test_vec_sub_u16x8, u16x8,
6071    [0, 0, 1, 2, 0, 0, 1, 2],
6072    [2, 1, 0, 0, 2, 1, 0, 0],
6073    [65534, 65535, 1, 2, 65534, 65535, 1, 2] }
6074
6075    test_vec_sub! { test_vec_sub_i8x16, i8x16,
6076    [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6077    [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6078    [-3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4] }
6079
6080    test_vec_sub! { test_vec_sub_u8x16, u8x16,
6081    [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6082    [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6083    [254, 255, 1, 2, 254, 255, 1, 2, 254, 255, 1, 2, 254, 255, 1, 2] }
6084
6085    macro_rules! test_vec_subs {
6086        { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6087            test_vec_2! {$name, vec_subs, $ty, [$($a),+], [$($b),+], [$($d),+] }
6088        }
6089    }
6090
6091    test_vec_subs! { test_vec_subs_i32x4, i32x4,
6092    [-1, 0, 1, 2],
6093    [2, 1, -1, -2],
6094    [-3, -1, 2, 4] }
6095
6096    test_vec_subs! { test_vec_subs_u32x4, u32x4,
6097    [0, 0, 1, 2],
6098    [2, 1, 0, 0],
6099    [0, 0, 1, 2] }
6100
6101    test_vec_subs! { test_vec_subs_i16x8, i16x8,
6102    [-1, 0, 1, 2, -1, 0, 1, 2],
6103    [2, 1, -1, -2, 2, 1, -1, -2],
6104    [-3, -1, 2, 4, -3, -1, 2, 4] }
6105
6106    test_vec_subs! { test_vec_subs_u16x8, u16x8,
6107    [0, 0, 1, 2, 0, 0, 1, 2],
6108    [2, 1, 0, 0, 2, 1, 0, 0],
6109    [0, 0, 1, 2, 0, 0, 1, 2] }
6110
6111    test_vec_subs! { test_vec_subs_i8x16, i8x16,
6112    [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6113    [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6114    [-3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4, -3, -1, 2, 4] }
6115
6116    test_vec_subs! { test_vec_subs_u8x16, u8x16,
6117    [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6118    [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6119    [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2] }
6120
6121    macro_rules! test_vec_min {
6122        { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6123            #[simd_test(enable = "altivec")]
6124            fn $name() {
6125                let a: s_t_l!($ty) = $ty::new($($a),+).into();
6126                let b: s_t_l!($ty) = $ty::new($($b),+).into();
6127
6128                let d = $ty::new($($d),+);
6129                let r = $ty::from(unsafe { vec_min(a, b) });
6130                assert_eq!(d, r);
6131            }
6132         }
6133    }
6134
6135    test_vec_min! { test_vec_min_i32x4, i32x4,
6136    [-1, 0, 1, 2],
6137    [2, 1, -1, -2],
6138    [-1, 0, -1, -2] }
6139
6140    test_vec_min! { test_vec_min_u32x4, u32x4,
6141    [0, 0, 1, 2],
6142    [2, 1, 0, 0],
6143    [0, 0, 0, 0] }
6144
6145    test_vec_min! { test_vec_min_i16x8, i16x8,
6146    [-1, 0, 1, 2, -1, 0, 1, 2],
6147    [2, 1, -1, -2, 2, 1, -1, -2],
6148    [-1, 0, -1, -2, -1, 0, -1, -2] }
6149
6150    test_vec_min! { test_vec_min_u16x8, u16x8,
6151    [0, 0, 1, 2, 0, 0, 1, 2],
6152    [2, 1, 0, 0, 2, 1, 0, 0],
6153    [0, 0, 0, 0, 0, 0, 0, 0] }
6154
6155    test_vec_min! { test_vec_min_i8x16, i8x16,
6156    [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6157    [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6158    [-1, 0, -1, -2, -1, 0, -1, -2, -1, 0, -1, -2, -1, 0, -1, -2] }
6159
6160    test_vec_min! { test_vec_min_u8x16, u8x16,
6161    [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6162    [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6163    [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }
6164
6165    macro_rules! test_vec_max {
6166        { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
6167            #[simd_test(enable = "altivec")]
6168            fn $name() {
6169                let a: s_t_l!($ty) = $ty::new($($a),+).into();
6170                let b: s_t_l!($ty) = $ty::new($($b),+).into();
6171
6172                let d = $ty::new($($d),+);
6173                let r = $ty::from(unsafe { vec_max(a, b) });
6174                assert_eq!(d, r);
6175            }
6176         }
6177    }
6178
6179    test_vec_max! { test_vec_max_i32x4, i32x4,
6180    [-1, 0, 1, 2],
6181    [2, 1, -1, -2],
6182    [2, 1, 1, 2] }
6183
6184    test_vec_max! { test_vec_max_u32x4, u32x4,
6185    [0, 0, 1, 2],
6186    [2, 1, 0, 0],
6187    [2, 1, 1, 2] }
6188
6189    test_vec_max! { test_vec_max_i16x8, i16x8,
6190    [-1, 0, 1, 2, -1, 0, 1, 2],
6191    [2, 1, -1, -2, 2, 1, -1, -2],
6192    [2, 1, 1, 2, 2, 1, 1, 2] }
6193
6194    test_vec_max! { test_vec_max_u16x8, u16x8,
6195    [0, 0, 1, 2, 0, 0, 1, 2],
6196    [2, 1, 0, 0, 2, 1, 0, 0],
6197    [2, 1, 1, 2, 2, 1, 1, 2] }
6198
6199    test_vec_max! { test_vec_max_i8x16, i8x16,
6200    [-1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2, -1, 0, 1, 2],
6201    [2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2, 2, 1, -1, -2],
6202    [2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }
6203
6204    test_vec_max! { test_vec_max_u8x16, u8x16,
6205    [0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2],
6206    [2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
6207    [2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }
6208
6209    macro_rules! test_vec_perm {
6210        {$name:ident,
6211         $shorttype:ident, $longtype:ident,
6212         [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
6213            #[simd_test(enable = "altivec")]
6214            fn $name() {
6215                let a = $longtype::from($shorttype::new($($a),+));
6216                let b = $longtype::from($shorttype::new($($b),+));
6217                let c = vector_unsigned_char::from(u8x16::new($($c),+));
6218                let d = $shorttype::new($($d),+);
6219
6220                let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
6221                assert_eq!(d, r);
6222            }
6223        }
6224    }
6225
6226    test_vec_perm! {test_vec_perm_u8x16,
6227    u8x16, vector_unsigned_char,
6228    [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
6229    [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
6230    [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6231     0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6232    [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
6233    test_vec_perm! {test_vec_perm_i8x16,
6234    i8x16, vector_signed_char,
6235    [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
6236    [100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
6237    [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6238     0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6239    [0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
6240
6241    test_vec_perm! {test_vec_perm_m8x16,
6242    m8x16, vector_bool_char,
6243    [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false],
6244    [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true],
6245    [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6246     0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6247    [false, false, true, true, false, false, true, true, false, false, true, true, false, false, true, true]}
6248    test_vec_perm! {test_vec_perm_u16x8,
6249    u16x8, vector_unsigned_short,
6250    [0, 1, 2, 3, 4, 5, 6, 7],
6251    [10, 11, 12, 13, 14, 15, 16, 17],
6252    [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6253     0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6254    [0, 10, 1, 11, 2, 12, 3, 13]}
6255    test_vec_perm! {test_vec_perm_i16x8,
6256    i16x8, vector_signed_short,
6257    [0, 1, 2, 3, 4, 5, 6, 7],
6258    [10, 11, 12, 13, 14, 15, 16, 17],
6259    [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6260     0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6261    [0, 10, 1, 11, 2, 12, 3, 13]}
6262    test_vec_perm! {test_vec_perm_m16x8,
6263    m16x8, vector_bool_short,
6264    [false, false, false, false, false, false, false, false],
6265    [true, true, true, true, true, true, true, true],
6266    [0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
6267     0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
6268    [false, true, false, true, false, true, false, true]}
6269
6270    test_vec_perm! {test_vec_perm_u32x4,
6271    u32x4, vector_unsigned_int,
6272    [0, 1, 2, 3],
6273    [10, 11, 12, 13],
6274    [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6275     0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6276    [0, 10, 1, 11]}
6277    test_vec_perm! {test_vec_perm_i32x4,
6278    i32x4, vector_signed_int,
6279    [0, 1, 2, 3],
6280    [10, 11, 12, 13],
6281    [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6282     0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6283    [0, 10, 1, 11]}
6284    test_vec_perm! {test_vec_perm_m32x4,
6285    m32x4, vector_bool_int,
6286    [false, false, false, false],
6287    [true, true, true, true],
6288    [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6289     0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6290    [false, true, false, true]}
6291    test_vec_perm! {test_vec_perm_f32x4,
6292    f32x4, vector_float,
6293    [0.0, 1.0, 2.0, 3.0],
6294    [1.0, 1.1, 1.2, 1.3],
6295    [0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
6296     0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
6297    [0.0, 1.0, 1.0, 1.1]}
6298
6299    #[simd_test(enable = "altivec")]
6300    fn test_vec_madds() {
6301        let a = vector_signed_short::from(i16x8::new(
6302            0 * 256,
6303            1 * 256,
6304            2 * 256,
6305            3 * 256,
6306            4 * 256,
6307            5 * 256,
6308            6 * 256,
6309            7 * 256,
6310        ));
6311        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6312        let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6313
6314        let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21);
6315
6316        assert_eq!(d, i16x8::from(unsafe { vec_madds(a, b, c) }));
6317    }
6318
6319    #[simd_test(enable = "altivec")]
6320    fn test_vec_madd_float() {
6321        let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
6322        let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
6323        let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
6324        let d = f32x4::new(
6325            0.1 * 0.1 + 0.1,
6326            0.2 * 0.2 + 0.2,
6327            0.3 * 0.3 + 0.3,
6328            0.4 * 0.4 + 0.4,
6329        );
6330
6331        assert_eq!(d, f32x4::from(unsafe { vec_madd(a, b, c) }));
6332    }
6333
6334    #[simd_test(enable = "altivec")]
6335    fn test_vec_nmsub_float() {
6336        let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
6337        let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
6338        let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
6339        let d = f32x4::new(
6340            -(0.1 * 0.1 - 0.1),
6341            -(0.2 * 0.2 - 0.2),
6342            -(0.3 * 0.3 - 0.3),
6343            -(0.4 * 0.4 - 0.4),
6344        );
6345        assert_eq!(d, f32x4::from(unsafe { vec_nmsub(a, b, c) }));
6346    }
6347
6348    #[simd_test(enable = "altivec")]
6349    fn test_vec_mradds() {
6350        let a = vector_signed_short::from(i16x8::new(
6351            0 * 256,
6352            1 * 256,
6353            2 * 256,
6354            3 * 256,
6355            4 * 256,
6356            5 * 256,
6357            6 * 256,
6358            7 * 256,
6359        ));
6360        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6361        let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
6362
6363        let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX);
6364
6365        assert_eq!(d, i16x8::from(unsafe { vec_mradds(a, b, c) }));
6366    }
6367
6368    macro_rules! test_vec_mladd {
6369        {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident,
6370            [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
6371            #[simd_test(enable = "altivec")]
6372            fn $name() {
6373                let a = $la::from($sa::new($($a),+));
6374                let b = $lbc::from($sbc::new($($b),+));
6375                let c = $sbc::new($($c),+).into();
6376                let d = $sd::new($($d),+);
6377
6378                assert_eq!(d, $sd::from(unsafe { vec_mladd(a, b, c) }));
6379            }
6380        }
6381    }
6382
6383    test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8,
6384        [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6385    }
6386    test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_signed_short, i16x8,
6387        [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6388    }
6389    test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8,
6390        [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6391    }
6392    test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_signed_short, i16x8,
6393        [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
6394    }
6395
6396    #[simd_test(enable = "altivec")]
6397    fn test_vec_msum_unsigned_char() {
6398        let a =
6399            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6400        let b = vector_unsigned_char::from(u8x16::new(
6401            255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
6402        ));
6403        let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
6404        let d = u32x4::new(
6405            (0 + 1 + 2 + 3) * 255 + 0,
6406            (4 + 5 + 6 + 7) * 255 + 1,
6407            (0 + 1 + 2 + 3) * 255 + 2,
6408            (4 + 5 + 6 + 7) * 255 + 3,
6409        );
6410
6411        assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) }));
6412    }
6413
6414    #[simd_test(enable = "altivec")]
6415    fn test_vec_msum_signed_char() {
6416        let a = vector_signed_char::from(i8x16::new(
6417            0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7,
6418        ));
6419        let b =
6420            vector_unsigned_char::from(u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
6421        let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6422        let d = i32x4::new(
6423            (0 - 1 + 2 - 3) + 0,
6424            (0) + 1,
6425            (0 + 1 + 2 + 3) + 2,
6426            (4 - 5 - 6 - 7) + 3,
6427        );
6428
6429        assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) }));
6430    }
6431
6432    #[simd_test(enable = "altivec")]
6433    fn test_vec_msum_unsigned_short() {
6434        let a = vector_unsigned_short::from(u16x8::new(
6435            0 * 256,
6436            1 * 256,
6437            2 * 256,
6438            3 * 256,
6439            4 * 256,
6440            5 * 256,
6441            6 * 256,
6442            7 * 256,
6443        ));
6444        let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6445        let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
6446        let d = u32x4::new(
6447            (0 + 1) * 256 * 256 + 0,
6448            (2 + 3) * 256 * 256 + 1,
6449            (4 + 5) * 256 * 256 + 2,
6450            (6 + 7) * 256 * 256 + 3,
6451        );
6452
6453        assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) }));
6454    }
6455
6456    #[simd_test(enable = "altivec")]
6457    fn test_vec_msum_signed_short() {
6458        let a = vector_signed_short::from(i16x8::new(
6459            0 * 256,
6460            -1 * 256,
6461            2 * 256,
6462            -3 * 256,
6463            4 * 256,
6464            -5 * 256,
6465            6 * 256,
6466            -7 * 256,
6467        ));
6468        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6469        let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6470        let d = i32x4::new(
6471            (0 - 1) * 256 * 256 + 0,
6472            (2 - 3) * 256 * 256 + 1,
6473            (4 - 5) * 256 * 256 + 2,
6474            (6 - 7) * 256 * 256 + 3,
6475        );
6476
6477        assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) }));
6478    }
6479
6480    #[simd_test(enable = "altivec")]
6481    fn test_vec_msums_unsigned() {
6482        let a = vector_unsigned_short::from(u16x8::new(
6483            0 * 256,
6484            1 * 256,
6485            2 * 256,
6486            3 * 256,
6487            4 * 256,
6488            5 * 256,
6489            6 * 256,
6490            7 * 256,
6491        ));
6492        let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6493        let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
6494        let d = u32x4::new(
6495            (0 + 1) * 256 * 256 + 0,
6496            (2 + 3) * 256 * 256 + 1,
6497            (4 + 5) * 256 * 256 + 2,
6498            (6 + 7) * 256 * 256 + 3,
6499        );
6500
6501        assert_eq!(d, u32x4::from(unsafe { vec_msums(a, b, c) }));
6502    }
6503
6504    #[simd_test(enable = "altivec")]
6505    fn test_vec_msums_signed() {
6506        let a = vector_signed_short::from(i16x8::new(
6507            0 * 256,
6508            -1 * 256,
6509            2 * 256,
6510            -3 * 256,
6511            4 * 256,
6512            -5 * 256,
6513            6 * 256,
6514            -7 * 256,
6515        ));
6516        let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
6517        let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6518        let d = i32x4::new(
6519            (0 - 1) * 256 * 256 + 0,
6520            (2 - 3) * 256 * 256 + 1,
6521            (4 - 5) * 256 * 256 + 2,
6522            (6 - 7) * 256 * 256 + 3,
6523        );
6524
6525        assert_eq!(d, i32x4::from(unsafe { vec_msums(a, b, c) }));
6526    }
6527
6528    #[simd_test(enable = "altivec")]
6529    fn test_vec_sum2s() {
6530        let a = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6531        let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6532        let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3);
6533
6534        assert_eq!(d, i32x4::from(unsafe { vec_sum2s(a, b) }));
6535    }
6536
6537    #[simd_test(enable = "altivec")]
6538    fn test_vec_sum4s_unsigned_char() {
6539        let a =
6540            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6541        let b = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
6542        let d = u32x4::new(
6543            0 + 1 + 2 + 3 + 0,
6544            4 + 5 + 6 + 7 + 1,
6545            0 + 1 + 2 + 3 + 2,
6546            4 + 5 + 6 + 7 + 3,
6547        );
6548
6549        assert_eq!(d, u32x4::from(unsafe { vec_sum4s(a, b) }));
6550    }
6551    #[simd_test(enable = "altivec")]
6552    fn test_vec_sum4s_signed_char() {
6553        let a =
6554            vector_signed_char::from(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6555        let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6556        let d = i32x4::new(
6557            0 + 1 + 2 + 3 + 0,
6558            4 + 5 + 6 + 7 + 1,
6559            0 + 1 + 2 + 3 + 2,
6560            4 + 5 + 6 + 7 + 3,
6561        );
6562
6563        assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) }));
6564    }
6565    #[simd_test(enable = "altivec")]
6566    fn test_vec_sum4s_signed_short() {
6567        let a = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6568        let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
6569        let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3);
6570
6571        assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) }));
6572    }
6573
6574    #[simd_test(enable = "altivec")]
6575    fn test_vec_mule_unsigned_char() {
6576        let a =
6577            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6578        let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
6579
6580        assert_eq!(d, u16x8::from(unsafe { vec_mule(a, a) }));
6581    }
6582
6583    #[simd_test(enable = "altivec")]
6584    fn test_vec_mule_signed_char() {
6585        let a = vector_signed_char::from(i8x16::new(
6586            0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
6587        ));
6588        let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
6589
6590        assert_eq!(d, i16x8::from(unsafe { vec_mule(a, a) }));
6591    }
6592
6593    #[simd_test(enable = "altivec")]
6594    fn test_vec_mule_unsigned_short() {
6595        let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6596        let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
6597
6598        assert_eq!(d, u32x4::from(unsafe { vec_mule(a, a) }));
6599    }
6600
6601    #[simd_test(enable = "altivec")]
6602    fn test_vec_mule_signed_short() {
6603        let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
6604        let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
6605
6606        assert_eq!(d, i32x4::from(unsafe { vec_mule(a, a) }));
6607    }
6608
6609    #[simd_test(enable = "altivec")]
6610    fn test_vec_mulo_unsigned_char() {
6611        let a =
6612            vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
6613        let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
6614
6615        assert_eq!(d, u16x8::from(unsafe { vec_mulo(a, a) }));
6616    }
6617
6618    #[simd_test(enable = "altivec")]
6619    fn test_vec_mulo_signed_char() {
6620        let a = vector_signed_char::from(i8x16::new(
6621            0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
6622        ));
6623        let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
6624
6625        assert_eq!(d, i16x8::from(unsafe { vec_mulo(a, a) }));
6626    }
6627
6628    #[simd_test(enable = "altivec")]
6629    fn test_vec_mulo_unsigned_short() {
6630        let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
6631        let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
6632
6633        assert_eq!(d, u32x4::from(unsafe { vec_mulo(a, a) }));
6634    }
6635
6636    #[simd_test(enable = "altivec")]
6637    fn test_vec_mulo_signed_short() {
6638        let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
6639        let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
6640
6641        assert_eq!(d, i32x4::from(unsafe { vec_mulo(a, a) }));
6642    }
6643
6644    #[simd_test(enable = "altivec")]
6645    fn vec_add_i32x4_i32x4() {
6646        let x = i32x4::new(1, 2, 3, 4);
6647        let y = i32x4::new(4, 3, 2, 1);
6648        let x = vector_signed_int::from(x);
6649        let y = vector_signed_int::from(y);
6650        let z = unsafe { vec_add(x, y) };
6651        assert_eq!(i32x4::splat(5), i32x4::from(z));
6652    }
6653
6654    #[simd_test(enable = "altivec")]
6655    fn vec_ctf_u32() {
6656        let v = vector_unsigned_int::from(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42));
6657        let v2 = unsafe { vec_ctf::<1, _>(v) };
6658        let r2 = vector_float::from(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0));
6659        let v4 = unsafe { vec_ctf::<2, _>(v) };
6660        let r4 = vector_float::from(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5));
6661        let v8 = unsafe { vec_ctf::<3, _>(v) };
6662        let r8 = vector_float::from(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25));
6663
6664        let check = |a, b| {
6665            let r =
6666                m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
6667            let e = m32x4::new(true, true, true, true);
6668            assert_eq!(e, r);
6669        };
6670
6671        check(v2, r2);
6672        check(v4, r4);
6673        check(v8, r8);
6674    }
6675
6676    #[simd_test(enable = "altivec")]
6677    fn test_vec_ctu() {
6678        let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42);
6679        let v2 = u32x4::from(unsafe {
6680            vec_ctu::<1>(vector_float::from(f32x4::new(
6681                0.0,
6682                2147483600.0,
6683                2147483600.0,
6684                21.0,
6685            )))
6686        });
6687        let v4 = u32x4::from(unsafe {
6688            vec_ctu::<2>(vector_float::from(f32x4::new(
6689                0.0,
6690                1073741800.0,
6691                1073741800.0,
6692                10.5,
6693            )))
6694        });
6695        let v8 = u32x4::from(unsafe {
6696            vec_ctu::<3>(vector_float::from(f32x4::new(
6697                0.0,
6698                536870900.0,
6699                536870900.0,
6700                5.25,
6701            )))
6702        });
6703
6704        assert_eq!(v2, v);
6705        assert_eq!(v4, v);
6706        assert_eq!(v8, v);
6707    }
6708
6709    #[simd_test(enable = "altivec")]
6710    fn vec_ctf_i32() {
6711        let v = vector_signed_int::from(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42));
6712        let v2 = unsafe { vec_ctf::<1, _>(v) };
6713        let r2 = vector_float::from(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0));
6714        let v4 = unsafe { vec_ctf::<2, _>(v) };
6715        let r4 = vector_float::from(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5));
6716        let v8 = unsafe { vec_ctf::<3, _>(v) };
6717        let r8 = vector_float::from(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25));
6718
6719        let check = |a, b| {
6720            let r =
6721                m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
6722            println!("{:?} {:?}", a, b);
6723            let e = m32x4::new(true, true, true, true);
6724            assert_eq!(e, r);
6725        };
6726
6727        check(v2, r2);
6728        check(v4, r4);
6729        check(v8, r8);
6730    }
6731
6732    #[simd_test(enable = "altivec")]
6733    fn test_vec_cts() {
6734        let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42);
6735        let v2 = i32x4::from(unsafe {
6736            vec_cts::<1>(transmute(f32x4::new(
6737                -1073741800.0,
6738                1073741800.0,
6739                1073741800.0,
6740                21.0,
6741            )))
6742        });
6743        let v4 = i32x4::from(unsafe {
6744            vec_cts::<2>(transmute(f32x4::new(
6745                -536870900.0,
6746                536870900.0,
6747                536870900.0,
6748                10.5,
6749            )))
6750        });
6751        let v8 = i32x4::from(unsafe {
6752            vec_cts::<3>(transmute(f32x4::new(
6753                -268435460.0,
6754                268435460.0,
6755                268435460.0,
6756                5.25,
6757            )))
6758        });
6759
6760        assert_eq!(v2, v);
6761        assert_eq!(v4, v);
6762        assert_eq!(v8, v);
6763    }
6764
6765    test_vec_2! { test_vec_rl, vec_rl, u32x4,
6766        [0x12345678, 0x9ABCDEF0, 0x0F0F0F0F, 0x12345678],
6767        [4, 8, 12, 68],
6768        [0x23456781, 0xBCDEF09A, 0xF0F0F0F0, 0x23456781]
6769    }
6770}
core/stdarch/crates/core_arch/src/powerpc/altivec.rs

core/stdarch/crates/core_arch/src/powerpc/
altivec.rs
